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参数资料
| 型号： | VNCLO-PSU-EU |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 14/25页 |
| 文件大小： | 0K |
| 描述： | POWER SUPPLY FOR VNCLO-MB1A EU |
| 应用说明： | Vinco LCD Interface Example Vinco Graphics Display Example Vinco Volt Meter Example Using the Vinco Libraries |
| 产品变化通告： | Name Change to Vinco 22/Apr/2011 |
| 特色产品： | Vinco Development Board |
| 标准包装： | 1 |
| 系列： | Vinco |
| 附件类型： | 电源 |
| 适用于相关产品： | FTDI Vinco 卡 |
| 其它名称： | 768-1093 |
Document Reference No.: FT_000327
Vinco Development Module Datasheet Version 2.01
Clearance No.: FTDI#173
4.2 Serial Peripheral Interface (SPI)
The VNC2-64Q has one master module and two slave modules. These modules are described more fully in
a VNC2 datasheet please refer to: -
4.2.1 Signal Description - SPI Slave
The SPI Slave signals can be programmed to a choice of available I/O pins. Table 4.2 explains the
available pins for each of the SPI Slave signals. This is a subset of what the VNC2-64Q is capable of to
avoid conflict with other functions on the Vinco module.
Available Pins
J2-1, J2-5, J3-2, J3-5, J4-6, J5-7, J6-1,
J6-5
J2-2, J2-6, J3-1, J3-6, J4-4, J5-1, J5-4,
J5-8, J6-2, J6-6
J1-1, J2-3, J3-3, J3-7, J4-1, J4-5, J5-2,
J5-5, J6-3, J6-7
J1-2, J2-4, J3-4, J3-8, J4-2, J4-3, J5-3,
J5-6, J6-4, J6-8
Name
spi_s0_clk
spi_s1_clk
spi_s0_mosi
spi_s1_mosi
spi_s0_miso
spi_s1_miso
spi_s0_ss#
spi_s1_ss#
Type
Input
Input/Output
Output
Input
Description
Slave clock input
Master Out Slave In
Synchronous data from master to slave
Master In Slave Out
Synchronous data from slave to master
Slave chip select
Table 4.2 – Data and Control Bus Signal Mode Options – SPI Slave
Note: # defines active low signals.
4.2.2 Signal Description - SPI Master
The SPI Master signals can be programmed to a choice of available I/O pins. Table 4.3 shows the SPI
master signals and the available pins that they can be mapped. This is a subset of what the VNC2-
64Q is capable of to avoid conflict with other functions on the Vinco module.
Available Pins
J2-1, J2-5, J3-2, J3-5, J4-6, J5-7, J6-1,
J6-5
J2-2, J2-6, J3-1, J3-6, J4-4, J5-1, J5-4,
J5-8, J6-2, J6-6
Name
spi_m_clk
spi_m_mosi
Type
Output
Output
Description
SPI master clock input
(J4-6 is the default)
Master Out Slave In
Synchronous data from master to slave
(J4-4 is the default)
J1-1, J2-3, J3-3, J3-7, J4-1, J4-5, J5-2,
J5-5, J6-3, J6-7
spi_m_miso
Input
Master In Slave Out
Synchronous data from slave to master
(J4-5 is the default)
J1-2, J2-4, J3-4, J3-8, J4-2, J4-3, J5-3,
J5-6, J6-4, J6-8
J2-1, J2-5, J3-2, J3-5, J4-6, J6,7, J6-1,
J6-5
spi_m_ss_0#
spi_m_ss_1#
Output
Output
Active low slave select 0 from master to slave
0
This SS# is used with the onboard ADC
Active low slave select 1 from master to slave
1
Table 4.3 – Data and Control Bus Signal Mode Options – SPI Master
Note: # defines active low signals.
Copyright ? 2012 Future Technology Devices International Limited
10
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相关代理商/技术参数 |
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|---|---|
| VNCLO-PSU-UK | 功能描述:插入式交流适配器 Vinco+9V/1A UK Power Supply Unit RoHS:否 制造商:Phihong 地区:Universal 安装风格:Wall, Interchangeable Plug 输入电压范围:90 VAC to 264 VAC 输出端数量:1 输出功率额定值:5 W 输出电压（通道 1）:5 V 输出电流（通道 1）:1 A 直流输出连接器:USB Type A 随附/必需的交流插头:Required 商用/医用:Commercial 效率:Level V |
| VNCLO-PSU-US | 制造商:FTDI 制造商全称:FTDI 功能描述:Vinculo Development Module |
| VNCLO-PSU-USA | 功能描述:插入式交流适配器 Vinco +9V/1A USA Pwr Supply Unit RoHS:否 制造商:Phihong 地区:Universal 安装风格:Wall, Interchangeable Plug 输入电压范围:90 VAC to 264 VAC 输出端数量:1 输出功率额定值:5 W 输出电压（通道 1）:5 V 输出电流（通道 1）:1 A 直流输出连接器:USB Type A 随附/必需的交流插头:Required 商用/医用:Commercial 效率:Level V |
| VNCLO-SHLD1A | 制造商:FTDI 制造商全称:FTDI 功能描述:Vinculo Development Module |
| VNCLO-SHLD-1A | 功能描述:模块配件 Vinco Prototyping Shield Accessory RoHS:否 制造商:Lantronix 产品: 用于: |
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