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| 型号： | VNCLO-PSU-USA |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 13/25页 |
| 文件大小： | 0K |
| 描述： | POWER SUPPLY FOR VNCLO-MB1A USA |
| 应用说明： | Vinco LCD Interface Example Vinco Graphics Display Example Vinco Volt Meter Example Using the Vinco Libraries |
| 产品变化通告： | Name Change to Vinco 22/Apr/2011 |
| 特色产品： | Vinco Development Board |
| 标准包装： | 1 |
| 系列： | Vinco |
| 附件类型： | 电源 |
| 适用于相关产品： | FTDI Vinco 卡 |
| 其它名称： | 768-1092 |
Document Reference No.: FT_000327
Vinco Development Module Datasheet Version 2.01
Clearance No.: FTDI#173
4
Configurable Pin outs
4.1 UART Interface
When the Vinco data and control buses are configured as a UART interface, the interface implements a
standard asynchronous serial UART port with flow control. The UART can support baud rates from
300baud to 6Mbaud. The UART interface is described in more detail in the Vinculum-II datasheet please
refer to: - FTDI website
4.1.1 Signal Description – UART Interface
The UART signals can be programmed to a choice of available I/O pins. Table 4.1 explains the available
pins for each of the UART signals. This is a subset of what the VNC2-64Q is capable of to avoid conflict
with other functions on the Vinco module.
Available Pins
J2-1, J2-5, J3-2, J3-5, J4-6, J5-7, J6-1,
J6-5
J2-2, J2-6, J3-1, J3-6, J4-4, J5-1, J5-4,
J5-8, J6-2, J6-6
J1-1, J2-3, J3-3, J3-7, J4-1, J4-5, J5-2,
J5-5, J6-3, J6-7
J1-2, J2-4, J3-4, J3-8, J4-2, J4-3, J5-3,
J5-6, J6-4, J6-8
J2-1, J2-5, J3-2, J3-5, J4-6, J6,7, J6-1,
J6-5
J2-2, J2-6, J3-1, J3-6, J4-4, J5-1, J5-4,
J5-8, J6-2, J6-6
J1-1, J2-3, J3-3, J3-7, J4-1, J4-5, J5-2,
J5-5, J6-3, J6-7
J1-2, J2-4, J3-4, J3-8, J4-2, J4-3, J5-3,
J5-6, J6-4, J6-8
Name
uart_txd
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
Type
Output
Input
Output
Input
Output
Input
Input
Input
Description
Transmit asynchronous data output
(Default J3-2)
Receive asynchronous data input (Default
J3-1)
Request To Send Control Output
Clear To Send Control Input
Data Acknowledge (Data Terminal Ready
Control) Output
Data Request (Data Set Ready Control)
Input
Data Carrier Detect Control Input
Ring Indicator Control Input. RI# low can
be used to resume the PC USB Host
controller from suspend.
Enable Transmit Data for RS485 designs.
TXDEN may be used to signal that a
J2-1, J2-5, J3-2, J3-5, J4-6, J5-7, J6-1,
J6-5
uart_tx_active
Output
transmit operation is in progress. The
TXDEN signal will be set high one bit-time
before data is transmitted and return low
one bit time after the last bit of a data
frame has been transmitted
Table 4.1 – Data and Control Bus Signal Mode Options – UART
Note: # defines active low signals.
Copyright ? 2012 Future Technology Devices International Limited
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| VNCLO-SHLD1A | 制造商:FTDI 制造商全称:FTDI 功能描述:Vinculo Development Module |
| VNCLO-SHLD-1A | 功能描述:模块配件 Vinco Prototyping Shield Accessory RoHS:否 制造商:Lantronix 产品: 用于: |
| VNCLO-START1 | 功能描述:界面开发工具 VINCO PLUS DEBUGGER PROGRAMMER MODULE RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| VND05 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:ISO HIGH SIDE SMART POWER SOLID STATE RELAY |
| VND05B | 功能描述:固态继电器-PCB安装 40V 1.6A Hi-Side SSR RoHS:否 制造商:Omron Electronics 控制电压范围: 负载电压额定值:40 V 负载电流额定值:120 mA 触点形式:1 Form A (SPST-NO) 输出设备:MOSFET 封装 / 箱体:USOP-4 安装风格:SMD/SMT |
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