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参数资料
| 型号： | VSC7216 |
| 厂商： | VITESSE SEMICONDUCTOR CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封装： | 27 MM, BGA-256 |
| 文件页数： | 2/12页 |
| 文件大小： | 321K |
| 代理商： | VSC7216 |
ESE
SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7216 Condensed
Multi-Gigabit Interconnect Chip
Page 10
VITESSE SEMICONDUCTOR CORPORATION
G52206-0, Rev. 2.0
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
6/23/99
16C, 15C
15D, 18A
17A, 15B
14D, 16A
RC(7:0)
O
TTL
Receive data for channel C. Synchronous to RCLKC/RCLKNC or
REFCLK as selected by RMODE(1:0), as are IDLEC, KCHC and ERRC.
20E, 18G
17G, 19F
20C, 17F
19D, 20B
RD(7:0)
O
TTL
Receive data for channel D. Synchronous to RCLKD/RCLKND or
REFCLK as selected by RMODE(1:0), as are IDLED, KCHD and ERRD.
17N
18W
17C
19H
IDLEA
IDLEB
IDLEC
IDLED
O
TTL
IDLE detect for channel n. When HIGH, an IDLE character has been
detected by the decoder and is on Rn(7:0)
When ENDEC=LOW, this is equivalent to COMDETn.
19P
16V
16D
18H
KCHA
KCHB
KCHC
KCHD
O
TTL
Kxx.x CHaracter detect for channel n. When HIGH, a special Kxx.x
character has been detected by the decoder and is on Rn(7:0)
When ENDEC=LOW, this is equivalent to data bit Rn8.
18N
16U
20A
20F
ERRA
ERRB
ERRC
ERRD
O
TTL
ERRor detect for channel n. When HIGH, an invalid 10-bit character or
disparity error has been detected and the data on Rn(7:0) is invalid.
When ENDEC=LOW, this is equivalent to data bit Rn9.
20M
19M
17T
20Y
18E
17E
17K
18K
RCLKA
RCLKNA
RCLKB
RCLKNB
RCLKC
RCLKNC
RCLKD
RCLKND
O
TTL
Recovered CLocK outputs for channel n. These outputs are driven from
either the channel A or channel n recovered clock, at 1/10 or 1/20 the baud
rate, as selected by RMODE(1:0) and DUAL. When unused, RCLKn is
LOW and RCLKNn is HIGH.
6U
4W
RMODE0
RMODE1
I
TTL
Receive output data timing MODE. Determines the timing reference for all
receive channels’ Rn(7:0), IDLEn, KCHn and ERRn output data, and also
for the PSDETn, RSDETn and TBERRn outputs, as defined in Table 5.
1U, 2U
1Y, 2Y
1A, 2A
1D, 2D
PRXA+/-
PRXB+/-
PRXC+/-
PRXD+/-
IPECL
Primary differential serial RX inputs for channel n. These pins receive the
serialized input data when LBENn(1) is LOW and RXP/Rn is HIGH,
otherwise they are unused. They are internally biased at VDD/2 through a
3.2K
resistor to the bias voltage. AC coupling is recommended.
1W, 2W
3Y, 4Y
3A, 4A
1B, 2B
RRXA+/-
RRXB+/-
RRXC+/-
RRXD+/-
IPECL
Redundant differential serial RX inputs for channel n. These pins receive
the serialized input data when LBENn(1) is LOW and RXP/Rn is LOW,
otherwise they are unused. They are internally biased at VDD/2 through a
3.2K
resistor to the bias voltage. AC coupling is recommended.
4P
3T
4R
3U
4F
3D
4G
3E
LBENA0
LBENA1
LBENB0
LBENB1
LBENC0
LBENC1
LBEND0
LBEND1
I
TTL
Loop Back ENable for channel n. These inputs control the channel serial or
parallel loopback configuration as described in Table 8.
Pin
Name
I/O
Type
Pin Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| VSC7216-01 | 制造商:VITESSE 制造商全称:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
| VSC7216-02 | 制造商:VITESSE 制造商全称:Vitesse Semiconductor Corporation 功能描述:02 Low Power Quad 1.25Gb/s Backplane Transceiver |
| VSC7216UC-01 | 制造商:VITESSE 制造商全称:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
| VSC7216UC-02 | 功能描述:IC TXRX BACKPLANE QUAD 256-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| VSC7216UC-06 | 功能描述:IC TXRX BACKPLANE QUAD 256-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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