
G52206-0, Rev. 2.0
VITESSE SEMICONDUCTOR CORPORATION
Page 11
6/23/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7216 Condensed
Multi-Gigabit Interconnect Chip
2V
3W
3B
2C
RXP/RA
RXP/RB
RXP/RC
RXP/RD
I
TTL
RX input Primary/Redundant serial input select for channel n. When
LBENn(1) is LOW, this input selects PRXn+/- as the RX serial input source
when HIGH and RRXn+/- as the serial input source when LOW.
20P
19V
18D
17J
PSDETA
PSDETB
PSDETC
PSDETD
O
TTL
Primary analog Signal DETect, channel n.
This output goes HIGH when
the amplitude on PRXn is greater than 400 mV, LOW when the
input is less than 200 mV. PSDETn is not defined when the input is
between 200 mV and 400 mV. Output timing is same as Rn(7:0).
17M
18U
19C
20J
RSDETA
RSDETB
RSDETC
RSDETD
O
TTL
Redundant analog Signal DETect, channel n.
This output goes HIGH
when the amplitude on RRXn is greater than 400 mV, LOW when
the input is less than 200 mV. RSDETn is not defined when the input
is between 200 mV and 400 mV. Output timing is same as Rn(7:0).
8A
9D
REFCLKP
REFCLKN
IPECL
REFCLK differential Positive and Negative PECL or single-ended TTL
inputs.
This rising edge of this clock latches transmit data and control
into the input register. It also provides the reference clock, at one
tenth or one twentieth of the baud rate to the PLL as selected by
DUAL. If TTL, connect to REFCLKP but leave REFCLKN open. If
PECL, connect both REFCLKP and REFCLKN.
1K
1L
CAP0
CAP1
Analog
Loop Filter CAPacitor for clock generation PLL, Nominally 0.1 uF,
amplitude is less than 3V.
5U
DUAL
I
TTL
DUAL clock Mode. When LOW, REFCLK and RCLKn/RCLKNn are 1/
10th the baud rate. When HIGH, they are 1/20th the baud rate.
13W
FLOCK
I
TTL
Frequency LOCKed mode. When HIGH indicates that each transmit
channel’s REFCLK is frequency-locked to the receive channel’s word
clock. Controls rate matching (IDLE delete/duplicate) logic along with the
WSI input as per Table 6.
12D
BIST
I
TTL
Built-In Self Test mode. When HIGH, all transmit channels continuously
send a 256 byte incrementing data pattern, and all receive channels signal
correct reception of the test pattern with a LOW on the TBERRn outputs.
12V
ENDEC
I
TTL
ENcoder/DECoder enable. When HIGH the VSC7216 is configured for 8
bit operation, internal 8B/10B encoding is enabled. When LOW a 10-bit
interface is used, internal 8B/10B encoding is bypassed.
12U
RESETN
I
TTL
RESETN input. When asserted LOW, the transmitter input skew buffers
and receiver elastic buffers are recentered, and the receiver LOS state
machines are forced to the LOS state.
20L
WSI
I
TTL
Word Sync Input. Used to control channel alignment and IDLE character
insertion/deletion as defined in Table 6.
17L
WSO
O
TTL
Word Sync Output. Used to set initial channel word alignment, and to
maintain alignment by controlling IDLE character insertion/deletion.
15A
TCK
I
TTL
JTAG Test Access Port test clock input
13B
TMS
I
TTL
JTAG Test Access Port test mode select input
14A
TDI
I
TTL
JTAG Test Access Port test data input
19K
TDO
O
TTL
JTAG Test Access Port test data output
13A
TRSTN
I
TTL
JTAG Test Access Port test logic reset input
Pin
Name
I/O
Type
Pin Description