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参数资料
| 型号： | W137H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系统时钟发生器 |
| 文件页数： | 8/13页 |
| 文件大小： | 141K |
| 代理商： | W137H |
W147G
PRELIMINARY
Document #: 38-07165 Rev. *A
Page 8 of 13
W147G Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a
“
0
”
level.
3. All register bits labeled
“
Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte
7 are reserved and must be written to
“
zero.
”
Note:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 0: Control Register (1 = Enable, 0= Disable)
[14]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Spread Spectrum (1=On/0=Off)
DOT
USB
CPU2_ITP
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
26
25
49
Byte 1: Control Register (1 = Enable, 0= Disable)
[14]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
36
37
39
40
42
43
45
46
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0= Disable)
[14]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pin Description
20
19
18
16
15
13
12
-
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
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