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参数资料
| 型号： | W149H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系统时钟发生器 |
| 文件页数： | 1/15页 |
| 文件大小： | 151K |
| 代理商： | W149H |
440BX AGPset Spread Spectrum Frequency Synthesizer
W149
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
November 16, 2000, rev. *B
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
Single chip system frequency synthesizer for Intel
440BX AGPset
Two copies of CPU output
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz output for SIO
Two buffered reference outputs
One IOAPIC output
Thirteen SDRAM outputs provide support for 3 DIMMs
Spread Spectrum feature always enabled
SMBus interface for programming
Power management control inputs
Smooth CPU frequency switching from 66.8–124 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
:.....................................................................3.3V±5%
V
DDQ2
:.....................................................................2.5V±5%
SDRAMIN to SDRAM0:12 Delay:..........................3.7 ns typ.
Table 1. Mode Input Table
[1]
Mode
0
1
Pin 2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS2
FS1
FS0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
CPU0:1
(MHz)
100
PCI_F, 1:5
(MHz)
33.3 (CPU/3)
(Reserved)
33.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
33.4 (CPU/2)
41.3 (CPU/3)
Spread
%
–0.5
100
103
66.8
83.3
66.8
124
±0.5
–0.5
–0.5
–0.5
±0.5
–0.5
Intel is a registered trademark of Intel Corporation.
Notes:
1.
Mode input latched at power-up.
2.
Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Logic Block Diagram
Pin Configuration
[2]
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
CPU0
PCI_F/MODE
PCI1
XTAL
OSC
PLL Ref Freq
PLL 1
X2
X1
VDDQ3
Stop
PCI2
PCI3
PCI4
48MHz/FS0
VDDQ3
PLL2
÷2/÷3
VDDQ2
VDDQ3
IOAPIC
PCI5
SMBus
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
CPU1
÷2
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
SCLK
W
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU0
CPU1
VDDQ2
OE
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SMBus
{
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