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参数资料
| 型号： | W1D64M72R8B-5AE-QA1 |
| 厂商： | XILINX INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | MO-237, DIMM-240 |
| 文件页数： | 10/11页 |
| 文件大小： | 255K |
| 代理商： | W1D64M72R8B-5AE-QA1 |
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
8
VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C<TOPR <+55°C, VOUT(DC) = VDDQ/2
-5
DDR2-400
-3.75
DDR2-533
Parameter
Symbol
MIN
MAX
MIN
MAX
Units
Active bank A to Active bank B command tRRD
7.5
-
7.5
-
ns
CAS A to CAS B command period
tCCD
2
tCK
Write recovery time
tWR
15
-
15
-
ns
Auto Precharge write recovery + Precharge
time
tDAL
WR+tRP
-
WR+tRP
-
tCK
Internal Write to Read command delay
tWTR
10
-
7.5
-
ns
Internal Read to Precharge command delay tRTP
7.5
-
7.5
-
ns
Exit precharge power down to any non-Read
command
tXP
2
-
2
-
tCK
Exit Self-Refresh to Read command
tXSRD
200
-
200
-
tCK
Exit Self-Refresh to non-Read command
tXSNR
tRFC+10
-
tRFC+10
-
ns
CKE minimum high and low pulse width
tCKE
3
-
3
-
tCK
Average periodic refresh interval
tREFI
-
7.8
-
7.8
s
OCD drive mode output delay
tOIT
0
12
0
12
ns
CKE low to CK, CK uncertainty
tDELAY
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
Note: These parameters are applicable for all 3 chip manufacturers, Micron, Infineon, and Samsung.
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