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参数资料
| 型号： | W207B-H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系统时钟发生器 |
| 文件页数： | 15/16页 |
| 文件大小： | 151K |
| 代理商： | W207B-H |
W207B
15
2.5V AC Electrical Characteristics
(CPU3.3#_2.5 Input = 1)
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5% (3.135
–
3.465V), V
DDQ2
= 2.5V±5% (2.375
–
2.625V),
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
Document #: 38-00847-B
CPU Clock Outputs, (Lump Capacitance Test Load = 20 pF)
Parameter
t
P
Description
Period
Test Condition/
Comments
Measured on rising edge at
1.25V
CPU = 66.6 MHz
CPU = 100 MHz
CPU = 133 MHz
Unit
ns
Min.
15
Typ.
Max.
Min.
10.0
Typ.
Max.
Min.
7.5
Typ.
Max.
t
H
High Time
Duration of clock cycle
above 2.0V
5.2
3.0
1.87
ns
t
L
Low Time
Duration of clock cycle
below 0.4V
5
2.8
1.67
ns
t
R
Output Rise
Edge Rate
Measured from 0.4V to
2.0V
0.8
3
0.8
3
0.8
3
V/ns
t
F
Output Fall
Edge Rate
Measured from 2.0V to
0.4V
0.8
3
0.8
3
0.8
3
V/ns
t
D
Duty Cycle
Measured on rising and
falling edge at 1.25V
45
55
45
55
45
55
%
t
JC
Jitter,
Cycle-to-Cycle
Measured on rising edge at
1.25V. Maximum differ-
ence of cycle time between
two adjacent cycles.
250
250
250
ps
t
SK
Output Skew
Measured on rising edge at
1.25V
175
175
175
ps
f
ST
Frequency Sta-
bilization from
Power-up (cold
start)
Assumes full supply volt-
age reached within 1 ms
from power-up. Short cy-
cles exist prior to frequen-
cy stabilization.
3
3
3
ms
Z
o
AC Output
Impedance
Average value during
switching transition. Used
for determining series ter-
mination value.
12
20
30
12
20
30
12
20
30
Ordering Information
Ordering Code
Package Name
H
Package Type
W207B
48-pin SSOP (300 mils)
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