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参数资料
| 型号： | W207B-H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系统时钟发生器 |
| 文件页数： | 6/16页 |
| 文件大小： | 151K |
| 代理商： | W207B-H |
W207B
6
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the
“
reserved
”
bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 4
gives the bit formats for registers located in Data
Bytes 0
–
6.
Table 5
details additional frequency selections that
are available through the serial data interface.
Table 4. Data Bytes 0
–
6 Serial Configuration Map
Bit(s)
Affected Pin
Pin No.
Control Function
Bit Control
Default
Pin Name
0
1
Data Byte 0
7
--
--
BYTE0_SEL3
Refer to
Table 5
0
6
--
--
BYTE0 _SEL2
Refer to
Table 5
0
5
--
--
BYTE0 _SEL1
Refer to
Table 5
0
4
--
--
BYTE0 _SEL0
Refer to
Table 5
0
3
--
--
FS0:3 override
Select operating fre-
quency by FS 3:0
Select operating fre-
quency by BYTE0_SEL
(3:0)
0
2
--
--
BYTE0_SEL4
Refer to
Table 5
0
1
--
--
(Reserved)
--
--
1
0
--
--
Test Mode
Normal
Three-state all outputs
0
Data Byte 1
7
--
--
SI0_SEL
48 MHz
24 MHz
1
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
43
CPU2
Clock Output Disable
Low
Active
1
2
45
CPU1
Clock Output Disable
Low
Active
1
1
46
CPU0
Clock Output Disable
Low
Active
1
0
--
--
(Reserved)
--
--
0
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
14
PCI6
Clock Output Disable
Low
Active
1
5
13
PCI5
Clock Output Disable
Low
Active
1
4
12
PCI4
Clock Output Disable
Low
Active
1
3
11
PCI3
Clock Output Disable
Low
Active
1
2
9
PCI2
Clock Output Disable
Low
Active
1
1
8
PCI1
Clock Output Disable
Low
Active
1
0
7
PCI0
Clock Output Disable
Low
Active
1
Data Byte 3
7
32
SDRAM7
Clock Output Disable
Low
Active
1
6
31
SDRAM6
Clock Output Disable
Low
Active
1
5
29
SDRAM5
Clock Output Disable
Low
Active
1
4
28
SDRAM4
Clock Output Disable
Low
Active
1
3
21
SDRAM3
Clock Output Disable
Low
Active
1
2
20
SDRAM2
Clock Output Disable
Low
Active
1
1
18
SDRAM1
Clock Output Disable
Low
Active
1
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