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参数资料
| 型号： | W218 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 2/17页 |
| 文件大小： | 175K |
| 代理商： | W218 |
W218
Document #: 38-07221 Rev. *A
Page 2 of 17
Pin Definitions
Pin Name
REF0/FSEL1
Pin No.
1
Pin
Type
I/O
Pin Description
Reference Clock:
3.3V 14.318-MHz clock output. This pin also serves as a strap
option for CPU frequency selection. See
Table 1
for detailed descriptions.
Crystal Input:
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output:
A connection for an external 14.318-MHz crystal. If using an ex-
ternal reference, this pin must be left unconnected.
PCI Clock 0 through 6:
3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via SMBus interface.
66-MHz Clock Output:
3.3V fixed 66-MHz clock.
X1
3
I
X2
4
O
PCI0_ICH,
PCI1:6
3V66_0:1/
3V66_AGP
USB
DOT
FSEL0,
Tristate#
PWR_DWN#
12, 13, 15, 16,
18, 19, 20
7, 8, 9
O
O
25
26
O
O
I
USB Clock Output:
3.3V fixed 48-MHz, non-spread spectrum USB clock output.
Dot Clock Output:
3.3V 48-MHz, non-spread spectrum signal.
Clock Function Selection pins:
LVTTL-compatible input to select device func-
tions. See
Table 1
for detailed descriptions.
Power-Down Control:
LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW. This input can be used as the
VTT_PWRGD input to support Intel
VRM 8.5 implementation.
CPU Clock Outputs:
Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the
configuration of SEL0:1 and SEL133. Voltage swing set by V
DDQ2
.
SDRAM Clock Outputs:
3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via SMBus interface.
28, 29
32
I
CPU2_ITP,
CPU0:1
49,52,50
O
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36,
34
55, 54
O
APIC0:1
O
Synchronous APIC Clock Outputs:
Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by V
DDQ2
.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection:
Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
3.3V Power Connection:
Power supply for core logic, PLL circuitry. Connect to
3.3V.
2.5V Power Connection:
Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDATA
SCLK
VDDQ3
30
31
I/O
I
P
2, 10, 11, 21, 27,
33, 38, 44
VDDA
22
P
VDDQ2
51, 53
P
GND
5, 6, 14, 17, 24,
35, 41, 47, 48,
56
23
G
GNDA
G
Ground Connections:
Ground for core logic, PLL circuitry.
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