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参数资料
| 型号： | W218 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 4/17页 |
| 文件大小： | 175K |
| 代理商： | W218 |
W218
Document #: 38-07221 Rev. *A
Page 4 of 17
How to use PD# input to support VTT_PWRGD
The PD# input can be used to support the VTT_PWRGD sig-
nal specified in the Intel
VRM 8.5 specification. The
VTT_PWRGD is used to indicated that the frequency select
output pins (BSEL[0:1]) from the CPU are valid and the clock
generator can use them to determine the CPU FSB frequency.
The assertion of PD# input pin during initial power up will delay
the start of the PLL, keep all the multiplexed I/O pins as input
and keep all the output inactive. The functionality of PD# will
allow system designer to use this input to support the
VTT_PWRGD output from the VRM 8.5 module. Please refer
to the
Figure 2
for power up sequence details.
3.3V & 2.5V
PD# (connected to
VTT_PWRGD)
Outputs
Input Latch
(pin 4 & pin21)
1 ms
PLL & Output
Synchronization
Figure 2. Power up sequence with PD# (VTT_PWRGD) hold LOW
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