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参数资料
| 型号： | W255HT |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | 200-MPz 24-Output Buffer for 4DDR or 3 SDRAM DIMMS |
| 中文描述： | 255 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 4/10页 |
| 文件大小： | 129K |
| 代理商： | W255HT |
W255
Document #: 38-07255 Rev. *C
Page 4 of 10
Maximum Ratings
Supply Voltage to Ground Potential..................
–
0.5 to +7.0V
DC Input Voltage (except BUF_IN)............
–
0.5V to V
DD
+0.5
Operating Conditions
[2]
Storage Temperature..................................
–
65
°
C to +150
°
C
Static Discharge Voltage ..........................................> 2000V
(per MIL-STD-883, Method 3015)
Switching Characteristics
[4]
Parameter
VDD3.3
VDD2.5
T
A
C
OUT
C
IN
Description
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
70
Unit
V
V
°
C
pF
pF
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
6
5
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
IH
I
IL
I
IH
I
OH
Description
Test Conditions
For all pins except SMBus
Min.
Typ.
Max.
0.8
Unit
V
V
μ
A
μ
A
mA
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
2.0
V
IN
= 0V
V
IN
= V
DD
V
DD
= 2.375V
V
OUT
= 1V
V
DD
= 2.375V
V
OUT
= 1.2V
I
OL
= 12 mA, V
DD
= 2.375V
I
OH
=
–
12 mA, V
DD
= 2.375V
Unloaded outputs, 133 MHz
50
50
–
18
–
32
I
OL
Output LOW Current
26
35
mA
V
OL
V
OH
I
DD
Output LOW Voltage
[3]
Output HIGH Voltage
[3]
Supply Current
[3]
(DDR-only mode)
Supply Current
(DDR-only mode)
Supply Current
Output Voltage Swing
0.6
V
1.7
V
400
mA
I
DD
Loaded outputs, 133 MHz
500
mA
I
DDS
V
OUT
PWR_DWN# = 0
See test circuity (refer to
Figure 1
)
100
μ
A
V
0.7
V
DD
+0.6
V
OC
Output Crossing Voltage
(V
DD
/2)
–
0.1
48
V
DD
/2
(V
DD
/2)
+0.1
52
V
IN
DC
Input Clock Duty Cycle
%
Parameter
–
–
Name
Test Conditions
Min.
66
IN
DC
–
5%
1.0
1.0
0.5
Typ.
Max.
200
IN
DC
+5%
2.75
2.75
1.50
Unit
MHz
%
Operating Frequency
Duty Cycle
[3, 5]
= t
2
÷
t
1
Measured at 1.4V for 3.3V outputs
Measured at V
DD
/2 for 2.5V outputs
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
Measured between 20% to 80% of
output (refer to
Figure 1
)
t
3
t
4
t
3d
SDRAM Rising Edge Rate
[3]
SDRAM Falling Edge Rate
[3]
DDR Rising Edge Rate
[3]
V/ns
V/ns
V/ns
Notes:
2.
3.
4.
5.
Multiple Supplies
: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
All parameters specified with loaded outputs.
Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
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