参数资料
型号: W255HT
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: 时钟及定时
英文描述: 200-MPz 24-Output Buffer for 4DDR or 3 SDRAM DIMMS
中文描述: 255 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48
封装: SSOP-48
文件页数: 5/10页
文件大小: 129K
代理商: W255HT
W255
Document #: 38-07255 Rev. *C
Page 5 of 10
Switching Waveforms
Duty Cycle Timing
t
4d
DDR Falling Edge Rate
[3]
Measured between 20% to 80% of
output (refer to
Figure 1
)
0.5
1.50
V/ns
t
5
t
6
Output to Output Skew for DDR
[3]
All outputs equally loaded
Output to Output Skew for
SDRAM
[3]
SDRAM Buffer LH Prop. Delay
[3]
SDRAM Buffer HL Prop. Delay
[3]
100
150
ps
ps
All outputs equally loaded
t
7
t
8
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
5
5
10
10
ns
ns
Switching Characteristics
(continued)
[4]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
t
1
t
2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t
4
Output-Output Skew
t
5
OUTPUT
OUTPUT
SDRAM Buffer HH and LL Propagation Delay
t
6
INPUT
OUTPUT
t
7
1.5V
1.5V
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