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| 型号： | W25Q16CVSFIG |
| 厂商： | Winbond Electronics |
| 文件页数： | 14/81页 |
| 文件大小： | 0K |
| 描述： | IC SPI FLASH 16MBIT 16SOIC |
| 标准包装： | 44 |
| 系列： | SpiFlash® |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 16M（2M x 8） |
| 速度： | 104MHz |
| 接口： | SPI 串行 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 其它名称： | W25Q16CVSFIG-ND W25Q16CVSFIGS |
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W25Q16CV
7.
STATUS REGISTERS AND INSTRUCTIONS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting
and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-
volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during
Standard/Dual SPI operations, the /WP pin.
7.1 STATUS REGISTERS
7.1.1
BUSY Status (BUSY)
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see t W , t PP , t SE , t BE , and
t CE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2
Write Enable Latch Status (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
7.1.3
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see t W in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
7.1.4
Top/Bottom Block Protect Bit (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
7.1.5
Sector/Block Protect Bit (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the
array as shown in the Status Register Memory Protection table. The default setting is SEC=0.
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相关代理商/技术参数 |
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| W25Q16CVSFIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVSNAG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVSNAP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVSNIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVSNIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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