W27C01
Publication Release Date: April 15, 2002
- 3 -
Revision A2
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C01 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
μ
F ceramic
capacitor connected between its V
DD
and Vss. This high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7
μ
F
electrolytic capacitor should be placed at the array's power supply connection between V
DD
and Vss.
The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
V
DD
= 5.0V
±
5%, Vpp = Vp
E
= V
HH
= 12V, V
CP
= V
PE
= 5V, X = V
IH
or V
IL
MODE
PINS
#CE
#OE
#PGM
A0
A9
V
DD
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
X
V
DD
V
DD
D
OUT
Output Disable
V
IL
V
IH
X
X
X
V
DD
V
DD
High Z
Standby (TTL)
V
IH
X
X
X
X
V
DD
V
DD
High Z
Standby (CMOS)
V
DD
±
0.3V
V
IL
X
X
X
X
V
DD
V
DD
High Z
Program
V
IH
V
IL
X
X
V
CP
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
V
CP
V
PP
D
OUT
Program Inhibit
V
IH
X
X
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
IL
V
PE
V
CP
V
PE
FF (Hex)
Erase Verify
V
IL
V
IL
V
IH
X
X
V
PE
V
PE
D
OUT
Erase Inhibit
V
IH
X
X
X
X
V
CP
V
PE
High Z
Product
Identifier-manufacturer
V
IL
V
IL
X
V
IL
V
HH
V
DD
V
DD
DA (Hex)
Product Identifier-device
V
IL
V
IL
X
V
IH
V
HH
V
DD
V
DD
01 (Hex)