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参数资料
| 型号： | W27E01 |
| 英文描述： | FPGA Fusion® Family 250K Gates Commercial 130nm (CMOS) Technology 1.5V 256-Pin FBGA |
| 中文描述： | 存储器 |
| 文件页数： | 7/15页 |
| 文件大小： | 257K |
| 代理商： | W27E01 |
Preliminary W27E01
Publication Release Date: May 30, 2002
- 7 -
Revision A1
12. READ OPERATION AC CHARACTERISTICS
(V
DD
= 5.0V
±
10 %, T
A
= 0 to 70
°
C)
W27E01-70
W27E01-90
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
T
RC
70
-
90
-
nS
Chip Enable Access Time
T
CE
-
70
-
90
nS
Address Access Time
T
ACC
-
70
-
90
nS
Output Enable Access Time
#OE High to High-Z Output
T
OE
-
30
-
40
nS
T
DF
-
25
-
25
nS
Output Hold from Address Change
T
OH
0
-
0
-
nS
Note: V
DD
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
13. AC PROGRAMMING/ERASE CHARACTERISTICS
(V
DD
= 3.3V
±
10 % or 5.0V
±
10 %, T
A
= 25
°
C)
LIMITS
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
V
PP
Setup Time
T
VPS
2.0
-
-
μ
S
μ
S
μ
S
μ
S
mS
Address Setup Time
T
AS
2.0
-
-
Data Setup Time
T
DS
2.0
-
-
#PGM Program Pulse Width
T
PWP
95
100
105
#PGM Erase Pulse Width
T
PWE
95
100
105
Data Hold Time
T
DH
2.0
-
-
μ
S
μ
S
nS
#OE Setup Time
T
OES
2.0
-
-
Data Valid from #OE
T
OEV
-
-
150
#OE High to Output High Z
T
DFP
0
-
130
nS
Address Hold Time after #PGM High
T
AH
0
-
-
μ
S
μ
S
μ
S
Address Hold Time (Erase)
T
AHE
2.0
-
-
#CE Setup Time
T
CES
2.0
-
-
Note: V
DD
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
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| W27E010 | 制造商:WINBOND 制造商全称:Winbond 功能描述:128K X 8 ELECTRICALLY ERASABLE EPROM |
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| W27E010-70 | 制造商:WINBOND 制造商全称:Winbond 功能描述:x8 EEPROM |
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