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参数资料
| 型号： | W28J321 |
| 英文描述： | FLASH |
| 中文描述： | 闪光 |
| 文件页数： | 3/48页 |
| 文件大小： | 416K |
| 代理商： | W28J321 |
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W28J320B/T
Publication Release Date: November 18, 2002
- 3 -
Revision A3
1. GENERAL DESCRIPTION
The W28J320B/T Flash memory chip is a high-density, cost-effective, nonvolatile, read/write storage
device suited for a wide range of applications. It operates of V
DD
= 2.7V to 3.6V, with V
PP
of 2.7V to
3.6V or 11.7V to 12.3V. This low voltage operation capability enbales use in low power applications.
The IC features a boot, parameter and main-blocked architecture, as well as low voltage and
extended cycling. These features provide a highly flexible device suitable for portable terminals and
personal computers. Additionally, the enhanced suspend capabilities provide an ideal solution for both
code and data storage applications. For secure code storage applications, such as networking where
code is either directly executed out of flash or downloaded to DRAM, the device offers four levels of
protection. These are: absolute protection, enabled when V
PP
≤
V
PPLK
; selective hardware blocking;
flexible software blocking; or write protection. These alternatives give designers comprehensive
control over their code security needs. The device is manufactured using 0.25
μ
m process technology.
It comes in industry-standard packaging, a 48-lead TSOP, which makes it ideal for small real estate
applications.
2. FEATURES
Low Voltage Operation
V
DD
= V
PP
= 2.7V to 3.6V Single Voltage
OTP(One Time Program) Block
3963 word + 4 word Program only array
User-Configurable
×
8 or
×
16 Operation
High-Performance Read Access Time
90 nS (V
DD
= 2.7V to 3.6V)
Operating Temperature
-40
°
C to +85
°
C
Low Power Management
4
μ
A Typical Standby Current
Automatic Power Savings Mode Decreases
I
CCR
in Static Mode
120
μ
A Typical Read Current
Optimized Array Blocking Architecture
Two 4k-word (8k-byte) Boot Blocks
Six 4k-word (8k-byte) Parameter Blocks
Sixty-three 32k-word (64k-byte) Main Blocks
Top or Bottom Boot Location
Extended Cycling Capability
Minimum of 100,000 Block Erase Cycles
Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
Enhanced Data Protection Features
Complete Protection with V
PP
≤
V
PPLK
Block Erase, Full Chip Erase, Word/Byte
Write and Lock-Bit Configuration Lockout
during Power Transitions
Block Locking with Command and #WP
Permanent Locking
Automated Block Erase, Full Chip Erase, Low
Power Management Word/Byte Write and
Lock-Bit Configuration
Command User Interface (CUI)
Status Register (SR)
SRAM-Compatible Write Interface
Industry-Standard Packaging
48-Lead TSOP
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