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参数资料
| 型号： | W28J321BB90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PBGA48 |
| 封装： | 8 X 11 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件页数： | 10/47页 |
| 文件大小： | 1385K |
| 代理商： | W28J321BB90L |
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W28J321B/T
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SR.5 being set to "1". Also, reliable full chip erasure can only occur when VDD = 2.7V to 3.6V and VPP =
VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If full chip
erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful full chip erase
requires for boot blocks that #WP is VIH and the corresponding block lock-bit be cleared. In parameter
and main blocks case, it must clear the corresponding block lock-bit. If all blocks are locked, SR.1 and
SR.5 will be set to "1".
Word Write Command
Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write that specifies the address and data (latched on
the rising edge of #WE). The WSM then takes over; controlling the word write and write verify
algorithms internally. After the word write sequence is written, the device automatically outputs status
register data when read (see Figure 8). The CPU can detect the completion of the word write event by
analyzing the status register bit SR.7.
When word write is complete, status register bit SR.4 should be checked. If word write error is
detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s
that do not successfully write to "0"s. The CUI remains in read status register mode until it receives
another command.
Reliable word writes can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence of this
high voltage, memory contents are protected against word writes. If word write is attempted while VPP
≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write for boot blocks
requires that #WP = VIH and the corresponding block lock-bit be cleared. In parameter and main
blocks case, the corresponding block lock-bit must be cleared. If word write is attempted under these
conditions, SR.1 and SR.4 will be set to "1".
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word write data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data when read after the Block Erase Suspend
command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1"). The period tWHR12 defines the block erase
suspend latency.
When Block Erase Suspend command writes to the CUI, if block erase is finished, the device is
placed in read array mode. Therefore, after Block Erase Suspend command writes to the CUI, Read
Status Register command (70H) has to write to CUI, and then status register bit SR.6 should be
checked to confirm that the device is in suspend mode. At this point, a Read Array command can be
written to read data from blocks other than that which is suspended.
To program data in other blocks, a Word Write command sequence can also be issued during erase
suspend. Using the Word Write Suspend command (reference the Word Write Suspend Command
subsection), a word write operation can also be suspended. During a word write operation with block
erase suspended, status register bit SR.7 will return to "0". However, SR.6 will remain "1" to indicate
block erase suspend status.
The only other valid commands while block erase is suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will
continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear. After the
Erase Resume command is written, the device automatically outputs status register data when read
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