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参数资料
| 型号： | W28J321BB90L |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 90 ns, PBGA48 |
| 封装： | 8 X 11 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件页数： | 11/47页 |
| 文件大小： | 1385K |
| 代理商： | W28J321BB90L |
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W28J321B/T
Publication Release Date: April 11, 2003
- 19 -
Revision A4
(see Figure 9). VPP must remain at VPPH1/2 (the same VPP level used for block erase) while block erase
is suspended. #RESET must also remain at VIH. #WP must also remain at VIL or VIH (the same #WP
level used for block erase). Block erase cannot resume until word write operations initiated during
block erase suspend have completed.
Word Write Suspend Command
The Word Write Suspend command allows word write interruption to read data in other flash memory
locations. Once the word write process starts, sending the Word Write Suspend command causes that
the WSM to suspend the Word write sequence at a predetermined point in the algorithm. The device
continues to output status register data when read after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine when the word write operation has been
suspended (both will be set to "1"). The period tWHR11 defines the word write suspend latency
parameters.
When Word Write Suspend command write to the CUI, if word write was finished, the device places
read array mode. Therefore, after Word Write Suspend command write to the CUI, Read Status
Register command (70H) has to write to CUI, then status register bit SR.2 should be checked to
confirm the device is in suspend mode.
At this point, a Read Array command can be written to read data from locations other than that which
is suspended. The only other valid commands while word write is suspended are Read Status
Register and Word Write Resume. After Word Write Resume command is written to the flash memory,
the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically
clear. After the Word Write Resume command is written, the device automatically outputs status
register data when read (see Figure 10). VPP must remain at VPPH1/2 (the same VPP level used for word
write) while in word write suspend mode. #RESET must also remain at VIH. #WP must also remain at
VIL or VIH (the same #WP level used for word write).
If the period from Word Write Resume command write to Word Write Suspend command write is too
short, it can be repeated, and the write time will be prolonged.
Set Block and Permanent Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a
permanent lock-bit and #WP pin. The block lock-bits and #WP pin gates program and erase
operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit
not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set
Permanent Lock-Bit command sets, sets the permanent lock-bit. After the permanent lock-bit is set,
block lock-bits and locked block contents cannot altered. Refer to Table 5 for a summary of hardware
and software write protection options.
Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set
block or permanent lock-bit setup along with appropriate block or device address is written followed by
either the set block lock-bit confirm (and an address within the block to be locked) or the set
permanent lock-bit confirm (and any device address). The WSM then executes the set lock-bit
algorithm. After the sequence is written, the device automatically outputs status register data when
read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the
status register bit SR.7.
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI will remain in read status register mode until
a new command is issued.
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