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参数资料
| 型号： | W28J800TT90L |
| 元件分类： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件页数： | 18/51页 |
| 文件大小： | 1468K |
| 代理商： | W28J800TT90L |
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W28J800B/T
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when V
DD
= 2.7V to
3.6V and V
PP
= V
PPH1/2
. In the absence of this high voltage, block contents are protected against
erasure. If full chip erase is attempted while V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to "1". Successful
full chip erase requires for boot blocks that #WP is V
IH
and the corresponding block lock-bit be
cleared. In parameter and main blocks case, it must clear the corresponding block lock-bit. If all blocks
are locked, SR.1 and SR.5 will be set to "1".
Word/Byte Write Command
Word/Byte write is executed by a two-cycle command sequence. Word/Byte write setup (standard
40H or alternate 10H) is written, followed by a second write that specifies the address and data
(latched on the rising edge of #WE). The WSM then takes over, controlling the word/byte write and
write verify algorithms internally. After the word/byte write sequence is written, the device
automatically outputs status register data when read (see Figure 7). The CPU can detect the
completion of the word/byte write event by analyzing the RY/#BY pin or status register bit SR.7.
When word/byte write is complete, status register bit SR.4 should be checked. If a word/byte write
error is detected, the status register should be cleared. The internal WSM verify only detects errors for
"1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it
receives another command.
Reliable word/byte writes can only occur when V
DD
= 2.7V to 3.6V and V
PP
= V
PPH1/2
. In the absence of
this high voltage, memory contents are protected against word/byte writes. If word/byte write is
attempted while V
PP
≤
V
PPLK
, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte
write for boot blocks requires that #WP = V
IH
and the corresponding block lock-bit be cleared. In
parameter and main blocks case, the corresponding block lock-bit must be cleared. If word/byte write
is attempted under these conditions, SR.1 and SR.4 will be set to "1".
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data that must be read after the Block Erase Suspend
command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1"). RY/#BY will also transition to High Z. The
period t
WHRZ2
defines the block erase suspend latency.
When Block Erase Suspend command writes to the CUI, if block erase is finished, the device is
placed in read array mode. Therefore, after Block Erase Suspend command writes to the CUI, Read
Status Register command (70H) has to write to CUI, and then status register bit SR.6 should be
checked to confirm that the device is in suspend mode. At this point, a Read Array command can be
written to read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued during erase suspend to program data in
other blocks. Using the Word/Byte Write Suspend command (see Word/Byte Write Suspend
Command section), a word/byte write operation can also be suspended. During a word/byte write
operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/#BY output
will transition to V
OL
. However, SR.6 will remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will
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