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参数资料
| 型号： | W29C042P-90 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 8 FLASH 5V PROM, 90 ns, PQCC32 |
| 封装： | PLASTIC, LCC-32 |
| 文件页数： | 16/22页 |
| 文件大小： | 297K |
| 代理商： | W29C042P-90 |
W29C042
Publication Release Date: February 18, 2002
- 3 -
Revision A2
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C042 is controlled by #CE and #OE, both Chip of which have to be low
for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the
chip is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high.
Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C042 is written (erased/programmed) on a page basis. Every page contains 256 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.
Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
S
after the initial byte-load cycle, the W29C042 will stay in the page load cycle. Additional bytes can then
be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program)
cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify the page address.
All bytes that are loaded into the page buffer must have the same page address. A0 to A7 specify the
byte address within the page. The bytes may be loaded in any order; sequential loading is not required.
In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written simultaneously
into the memory array. The typical write (erase/program) time is 5 mS. The entire memory array can be
written in 10.4 seconds. Before the completion of the internal write cycle, the host is free to perform
other tasks such as fetching data from other locations in the system to prepare to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a specific
address) to be performed before the data load operation. The three-byte load command sequence
begins the page load cycle, without which the write operation will not be activated. This write scheme
provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during
system power-up and power-down.
The W29C042 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
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