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参数资料
| 型号： | W3041BCL |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 11/12页 |
| 文件大小： | 822K |
| 代理商： | W3041BCL |
W3041
Preliminary Data Sheet
IF Receiver with Integrated IF2 Bandpass Filters
December 1998
8
Lucent Technologies Inc.
Enabling the Power Supply (No Direct Logic to Pin 20) (continued)
Example: Suppose the voltage regulator source resistance RS is 2
and the voltage regulator output filter
capacitor Cs is 3.3 F. The time constant
τ
R
is 2 * 3.3E
– 6 = 6.6 s. The voltage regulator output is specified as
3.0 ± 0.1 Vdc, so VR = 2.9 Vdc.
(
)
(
)s
6
E
2
.
21
616
.
0
9
.
2
5
.
2
1
ln
6
E
6
.
6
E
=
=
τ
Selecting practical values for components RE and CE using RECE = 21.2E
– 6 involves first selecting a standard
capacitor value for CE available in small physical size such as 1000 pF. The value for RE can then be found
from 21.2E-6 ÷ 1000E-12 = 21.2 k
for which the standard value 22 k can be chosen. Using these values in
an Excel* plot, the powerup time can be seen by inspection, as shown in Figure 5.
τ(VREG) = 6.6 s
τ(ENBL) = 21.2 s
0
0.5
1
1.5
2
2.5
3
3.5
0
0.00002
0.00004
0.00006
0.00008
0.0001
ELAPSED TIME (seconds)
VENBL
V(REGULATOR)
MAX. ENABLE TIME = 27 s TO
MAX VENBL = 2.1 Vdc
+ 12 s MAX FOR FILTER
CALIBRATION
= 39 s
Figure 5. Required Enable Delay for Filter Calibration Circuit
*Excel is a trademark of Microsoft Corporation.
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