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参数资料
| 型号： | W320-04H |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DRVR CPUOUT 200MHZ 56SSOP |
| 标准包装： | 26 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:22 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
W320-04
.......................Document #: 38-07010 Rev. *C Page 3 of 16
Function Table[1]
S2
S1
S0
CPU
(MHz)
3V66[0:1]
(MHz)
66BUFF[0:2]/
3V66[2:4]
(MHz)
66IN/3V66_5
(MHz)
PCI_F/PCI
(MHz)
REF0(MHz)
USB/DOT
(MHz)
Notes
1
0
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
1
0
1
100 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
1
0
200 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
1
133 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
0
66 MHz
33 MHz
14.318 MHz
48 MHz
0
1
100 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
0
1
0
200 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
0
1
133 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
Mid
0
Hi-Z
Mid
0
1
TCLK/2
TCLK/4
TCLK/8
TCLK
TCLK/2
Mid
1
0
Reserved
–
Mid
1
Reserved
–
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF = VDD/(3*Rr)
Output Current
VOH @ Z
050
Rr = 221 1%, IREF = 5.00 mA
IOH = 4*IREF
1.0V @ 50
150
Rr = 475 1%, IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Clock Driver Impedances
Impedance
Buffer Name
VDD Range
Buffer Type
Min.
Typ.
Max.
CPU, CPU#
Type X1
50
REF
3.135–3.465
Type 5
12
30
55
PCI, 3V66, 66BUFF
3.135–3.465
Type 5
12
30
55
USB
3.135–3.465
Type 3A
12
30
60
DOT
3.135–3.465
Type 3B
12
30
60
Clock Enable Configuration
PWR_DWN# CPU_STOP#
PCI_STOP#
CPU
CPU#
3V66
66BUFF
PCI_F
PCI
USB/DOT VCOS/ OSC
0
X
IREF*2
FLOAT
LOW
OFF
1
0
ON
FLOAT
ON
OFF
ON
1
0
1
ON
LOW
ON
1
0
ON
OFF
ON
11
1
ON
Note:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation
3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6. Required for DC output impedance verification.
7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
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|---|---|
| W320-04HT | 功能描述:时钟合成器/抖动清除器 200MHz Differential CPU Outputs RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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