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参数资料
| 型号： | W332M64V-125BC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 SYNCHRONOUS DRAM, 6 ns, PBGA219 |
| 封装： | 25 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 12/15页 |
| 文件大小： | 351K |
| 代理商： | W332M64V-125BC |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W332M64V-XBX
October 2006
Rev. 1
FIGURE. 4 – CAS LATENCY
OPERATING MODE
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
TABLE 2 – CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
CAS
LATENCY = 3
-100
≤ 75
≤ 100
-125
≤ 100
≤ 125
-133
≤ 100
≤ 133
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CLK
Command
I/O
CLK
Command
I/O
T0
T1
T2
T3
T0
T1
T2
T3
T4
READ
NOP
CAS Latency = 2
DOUT
tLZ
tOH
tAC
READ
NOP
DOUT
tLZ
tOH
tAC
CAS Latency = 3
DON'T CARE
UNDEFINED
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the rst piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
相关PDF资料 |
PDF描述 |
|---|---|
| W332M64V-100BI | 32M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA219 |
| W332M72V-100SBM | 32M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA208 |
| W332M72V-125SBC | 32M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA208 |
| W332M72V-100SBC | 32M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA208 |
| W332M72V-100SBM | 32M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W332M64V-125BI | 制造商:Microsemi Corporation 功能描述:32M X 64 SDRAM, 3.3V, 125MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W332M64V-125BM | 制造商:Microsemi Corporation 功能描述:32M X 64 SDRAM, 3.3V, 125MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W332M64V-125SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 SDRAM, 3.3V, 125MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W332M64V-125SBI | 制造商:Microsemi Corporation 功能描述:32M X 64 SDRAM, 3.3V, 125MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
| W332M64V-125SBM | 制造商:Microsemi Corporation 功能描述:32M X 64 SDRAM, 3.3V, 125MHZ, 208 PBGA, MIL-TEMP. - Bulk |
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