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参数资料
| 型号： | W3DG6430V10D2 |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封装： | DIMM-168 |
| 文件页数： | 5/6页 |
| 文件大小： | 154K |
| 代理商： | W3DG6430V10D2 |
February 2002
Rev. 0
W3DG6430V-D2
5
White Electronic Designs
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
PRELIMINARY
AC CHARACTERISTICS
133MHz component timing
Paramater
Symbol
Min
Max
Units
Notes
Access time from CLK
CL = 2
tAC
5.4
ns
Address hold time
tAH
0.8
ns
Address setup time
tAS
1.5
ns
CLK high level width
tCH
2.5
ns
CLK low level width
tCL
2.5
ns
Clock cycle time
CL = 2
tCK
7.5
ns
1
CKE hold time
tCKH
0.8
ns
CKE setup time
tCKS
1.5
ns
CS, RAS, CAS, WE, DQM hold time
tCMH
0.8
ns
CS, RAS, CAS, WE, DQM setup time
tCMS
1.5
ns
Data-in hold time
tDH
0.8
ns
Data-in setup time
tDS
1.5
ns
Data-out high-impedance time
CL = 2
tHZ
5.4
ns
2
Data-out low-impedance time
tLZ
1ns
Data-out hold time (load)
tOH
3ns
Data-out hold time (no load)
tN
1.8
ns
3
Active to Precharge command
tRAS
37
120,000
ns
Active to Active command period
tRC
60
ns
Active to Read or Write delay
tRCD
15
ns
Refresh period
tREF
64
ms
Auot refresh period
tRFC
66
ns
Precharge command period
tRP
15
ns
Active bank a to Active bank b command
tRRD
14
ns
Transition time
tT
0.3
1.2
ns
4
Write recovery time
tWR
1 CLK + 7ns
ns
5
ns
6
Exit Self Refresh to Active command
tXSR
67
ns
7
Notes:
1. The clock frequency must remain constant ( stable clock is dened as a signal cycling within
timing constraints specied for the clock pin) during access or precharge states (READ,
WRITE, including WR and Precharge commands). CKE may be used to reduce the data rate.
2. tHZ denes the time at which the output achieves the open circuit condition; it is not a reference
to VOH or VOL. The last valid data element will meet tOH before going High-Z.
3. Paramater guaranteed by design
4. AC characteristics assume tT = 1ns
5. Auto precharge mode only) The precharge timing budget ( tRP) begins 7ns after the rst clock
delay, after the last Write is executed.
6. Precharge mode only.
7. CLK must be toggled a minimum of two times during this period.
MODULE AC CHARACTERISTIC
Symbol
Min
Max
Units
Notes
Address hold time
AH
0
ns
Address setup time
AS
4.5
ns
CS, RAS, CAS, WE, DQM hold time
CMH
0
ns
CS, RAS, CAS, WE, DQM setup time
CMS
4.5
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3DG6430V-D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB - 32M x 64 BUFFERED SDRAM MODULE |
| W3DG6432V10D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB- 32Mx64 SDRAM UNBUFFERED |
| W3DG6432V75D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB- 32Mx64 SDRAM UNBUFFERED |
| W3DG6432V7D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB- 32Mx64 SDRAM UNBUFFERED |
| W3DG6432V-D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256MB- 32Mx64 SDRAM UNBUFFERED |
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