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参数资料
| 型号： | W3E232M16S-400STCG |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封装： | 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件页数： | 4/17页 |
| 文件大小： | 562K |
| 代理商： | W3E232M16S-400STCG |
W3E232M16S-400STCG
12
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
August 2007
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
AC INPUT OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C
Parameter/Condition
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
VIH (AC)
VREF +0.310
—
V
Input Low (Logic 0) Voltage
VIL (AC)
—VREF -0.310
V
IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TA +70°C
Parameter/Condition
Symbol
Max
Units
Notes
DDR400
OPERATING CURRENT: One bank; Active-Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control
inputs changing once every two clock cycles
IDD0*
125
mA
22, 47,
53
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
IDD1*
165
mA
22, 47,
53
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK=tCK (MIN); CKE
= (LOW)
IDD2P**
10
mA
23, 32,
49
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
IDD2F**
60
mA
50, 54
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK=tCK (MIN); CKE = (LOW)
IDD3P**
90
mA
23, 32,
49, 54
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA
IDD3N**
120
mA
22, 54
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA
IDD4R*
195
mA
22, 47,
53
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN) DQ, DM, and DQS
inputs changing twice per clock cycle
IDD4W*
220
mA
22, 53
AUTO REFRESH BURST CURRENT:
tREFC = tRFC(MIN)
IDD5**
440
mA
49, 54
SELF REFRESH CURRENT; CKE ≤0.2V
Standard
IDD6**
10
mA
11, 54
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed:
tCK=tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands
IDD7*
405
mA
22, 48,
53
IDD specications were calculated using
SAMSUNG components. Other Manufactures DRAMS may have different values
* One DRAM active at a time - second DRAM is in power down mode.
** Both DRAM operating in this condition.
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相关代理商/技术参数 |
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|---|---|
| W3E232M16S-400STI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-400STIG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-XSTX | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E32M64S-200BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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