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参数资料
| 型号： | W3E64M72S-333SBC |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| 封装： | 25 X 32 MM, PLASTIC, BGA-219 |
| 文件页数： | 17/19页 |
| 文件大小： | 496K |
| 代理商： | W3E64M72S-333SBC |
W3E64M72S-XSBX
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2007
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specications without notice.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM.
The SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses. Input data appearing on the DQ
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specied time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specic READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
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| W3E64M72S-333BC | 64M X 72 SYNCHRONOUS DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-250BM | 64M X 72 SYNCHRONOUS DRAM, 0.8 ns, PBGA219 |
| W3EG128M72ETSU262JD3 | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E64M72S-333SBI | 制造商:Microsemi Corporation 功能描述:W3E64M72S-333SBI - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3E64M72S-XBX | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3EG128M72ETSU202AJD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU202D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU202JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
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