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参数资料
| 型号： | W3EG6462S335D3 |
| 英文描述： | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 512MB的- 2x32Mx64 DDR SDRAM内存缓冲 |
| 文件页数： | 5/13页 |
| 文件大小： | 250K |
| 代理商： | W3EG6462S335D3 |
White Electronic Designs
W3EG6462S-D3
-JD3
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
May 2005
Rev. 4
ADVANCED
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
DDR400@
CL=3
Max
2200
DDR333@
CL=2.5-3-3
Max
1960
DDR266@
CL=2
Max
1800
DDR266@
CL=2.5
Max
1800
DDR200@
CL=2
Max
1800
Units
mA
Operating Current
I
DD1
2480
2320
2080
2080
2080
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
64
64
64
64
64
rnA
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t
=t
(MIN); DQ,DM and DQS
inputs changing once per clock cycle.
t
RC
= t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN);
t
=t
(MIN); Address and control
inputs change only during Active Read
or Write commands.
960
800
720
720
720
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
640
480
400
400
400
mA
I
DD3N
1120
960
800
800
800
mA
Operating Current
I
DD4R
2720
2360
2000
2000
2000
mA
Operating Current
I
DD4W
2680
2360
2000
2000
2000
rnA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
3200
64
4880
3000
64
4240
2680
64
3600
2680
64
3600
2680
64
3600
mA
mA
mA
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相关代理商/技术参数 |
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|---|---|
| W3EG6462S335JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S403D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S403JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S-D3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S-JD3 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
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