- 您现在的位置：买卖IC网 > PDF目录361781 > W3EG6467S-D4 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED PDF资料下载
参数资料
| 型号： | W3EG6467S-D4 |
| 英文描述： | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 512MB的- 2x32Mx64 DDR SDRAM内存缓冲 |
| 文件页数： | 5/12页 |
| 文件大小： | 207K |
| 代理商： | W3EG6467S-D4 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6467S-D4
January 2005
Rev. 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ T
A
≤ 70°C, V
CCQ
= 2.5V ±0.2V, V
CC
= 2.5V ±0.2V
Parameter
Symbol Conditions
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
One device bank; Active-Read-Precharge;
Burst = 2; t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
All device banks idle; Power- down mode;
t
CK
=t
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
One device bank active; Power-down mode;
t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX);
t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One
device bank active;Address and control
inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
I
DD5
t
RC
=t
RC
(MIN)
I
DD6
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR403
@CL=3
Max
DDR333
@CL=2.5
Max
1600
DDR266
@CL=2, 2.5
Max
1440
DDR200
@CL=2
Max
1360
Units
mA
Operating Current
I
DD0
Operating Current
I
DD1
1800
1640
1560
mA
Precharge Power-
Down Standby Current
I
DD2P
48
48
48
mA
Idle Standby Current
I
DD2F
400
320
320
mA
Active Power-Down
Standby Current
I
DD3P
560
480
480
mA
Active Standby Current
I
DD3N
880
720
720
mA
Operating Current
I
DD4R
2160
1840
1840
mA
Operating Current
I
DD4W
2160
1800
1800
mA
Auto Refresh Current
Self Refresh Current
2240
48
3120
2000
48
2960
2000
48
2720
mA
mA
mA
Operating Current
I
DD7A
相关PDF资料 |
PDF描述 |
|---|---|
| W3EG64M64ETSU335D4IMG | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4ISG | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4MG | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4SG | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU403D4IMG | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3EG64M64ETSU335D4IMG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4ISG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU335D4SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| W3EG64M64ETSU403D4IMG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
发布紧急采购，3分钟左右您将得到回复。