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参数资料
| 型号： | W3EG6467S-D4 |
| 英文描述： | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 512MB的- 2x32Mx64 DDR SDRAM内存缓冲 |
| 文件页数： | 7/12页 |
| 文件大小： | 207K |
| 代理商： | W3EG6467S-D4 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6467S-D4
January 2005
Rev. 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: V
CC
= V
CCQ
= +2.6V ± 0.1V
AC CHARACTERISTICS
PARAMETER
SYMBOL MIN
Access window of DQs from CK/CK#
t
AC
CK high-level width
t
CH
CK low-level width
t
CL
Clock cycle time
CL = 3
t
CK (3)
CL = 2.5
t
CK (2.5)
CL = 2
t
CK (2)
DQ and DM input hold time relative to DQS
t
DH
DQ and DM input setup time relative to DQS
t
DS
DQ and DM input pulse width (for each input)
t
DIPW
Access window of DQS from CK/CK#
t
DQSCK
DQS input high pulse width
t
DQSH
DQS input low pulse width
t
DQSL
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
t
DQSS
DQS falling edge to CK rising - setup time
t
DSS
DQS falling edge from CK rising - hold time
t
DSH
Half clock period
t
HP
Data-out high-impedance window from CK/CK#
t
HZ
Data-out low-impedance window from CK/CK#
t
LZ
Address and control input hold time (1 V/ns)
t
IHF
Address and control input setup time (1 V/ns)
t
ISF
Address and control input hold time (0.5 V/ns)
t
IHS
Address and control input setup time (0.5 V/ns)
t
ISS
Address and Control input pulse width (for each input)
t
IPW
LOAD MODE REGISTER command cycle time
t
MRD
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
t
QHS
ACTIVE to PRECHARGE command
t
RAS
ACTIVE to READ with Auto precharge command
t
RAP
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
t
RFC
ACTIVE to READ or WRITE delay
t
RCD
PRECHARGE command period
t
RP
DQS read preamble
t
RPRE
DQS read postamble
t
RPST
ACTIVE bank a to ACTIVE bank b command
t
RRD
DQS write preamble
t
WPRE
DQS write preamble setup time
t
WPRES
403
335
262
265
202
MAX
+0.7
0.55
0.55
7.5
13
13
MIN
-0.7
0.45
0.45
6
7.5
MAX
+0.7
0.55
0.55
13
13
MIN
-0.75 +0.75 -0.75
0.45
0.55
0.45
0.55
7.5
13
7.5
13
MAX
MIN
MAX
0.75
0.55
0.55
13
13
MIN
-0.8
0.45
0.45
8
10
MAX UNITS NOTES
0.8
ns
0.55
t
CK
0.55
t
CK
13
ns
13
ns
ns
ns
ns
ns
ns
t
CK
t
CK
0.6
ns
-0.7
0.45
0.45
5
6
7.5
0.4
0.4
1.75
-0.6
0.35
0.35
0.45
0.45
7.5
7.5/10
25
25
38, 43
38, 43
37, 42
22, 26
22, 26
26
0.45
0.45
1.75
-0.60 +0.60 -0.75 +0.75 +0.75
0.35
0.35
0.35
0.35
0.45
0.5
0.5
1.75
0.6
0.6
2
-0.8
0.35
0.35
0.5
+0.6
+0.8
t
DQSQ
0.40
0.5
22
0.72
0.2
0.2
1.28
0.75
0.2
0.2
1.25
0.75
0.2
0.2
1.25
0.75
0.2
0.2
1.25
0.75
0.2
0.2
1.25
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
29
+0.70
+0.70
+0.75
+0.75
+0.8
16, 35
16, 35
12
12
12
12
-0.70
0.6
0.6
0.6
0.6
2.20
2
t
HP
- t
QHS
-0.70
0.75
0.75
0.80
0.80
2.2
12
t
HP
- t
QHS
-0.75
0.90
0.90
1
1
2.2
15
t
HP
- t
QHS
-0.75
0.90
0.90
1
1
2.2
15
t
HP
- t
QHS
-0.8
ns
1.1
1.1
1.1
2.2
16
t
HP
- t
QHS
1.1
12
t
QH
22
0.50
70,000
0.60
70,000
0.75
120,000
0.75
120,000
1
ns
ns
ns
ns
40
15
55
42
15
60
40
15
60
40
20
65
40
20
70
120,000
30
t
RC
70
15
15
0.9
0.4
10
0.25
0
72
15
15
0.9
0.4
12
0.25
0
75
15
15
0.9
0.4
15
0.25
0
72
20
20
0.9
0.4
15
0.25
0
75
20
20
0.9
0.4
15
0.25
0
ns
ns
ns
t
CK
t
CK
ns
t
CK
ns
41
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
36
36
17, 19
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| W3EG64M64ETSU335D4IMG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
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| W3EG64M64ETSU335D4SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
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