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参数资料
| 型号： | W3EG64M64ETSU403D4SG |
| 英文描述： | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| 中文描述： | 512MB的- 64Mx64 DDR SDRAM，可缓冲，SO - DIMM插槽 |
| 文件页数： | 8/12页 |
| 文件大小： | 190K |
| 代理商： | W3EG64M64ETSU403D4SG |
WV3EG64M64ETSU-D4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ T
A
≤ +70°C;
AC Characteristics
Parameter
Symbol
Row Cycle Time
t
RC
Refresh row cycle time
t
RFC
Row active
t
RAS
RAS# to CAS# delay
t
RCD
Row percharge time
t
RP
Row active to row active delay
t
RRD
Write recovery time
t
WR
Last data in to READ command
t
WTR
CL = 2.5
t
CK
CL = 3
CK high-level width
t
CH
CK low-level width
t
CL
Access window of DQS from CK/CK#
t
DQSCK
Access window of DQs from CK/CK#
t
AC
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Read preamble
t
RPRE
Read postamble
t
RPST
CK to valid DQS-in
t
DQSS
DQS-in setup time
t
WPRES
DQS-in hold time
t
WPRE
DQS falling edge to CK rising-setup time
t
DSS
DQS falling edge to CK rising-hold time
t
DSH
Notes:
Industrial grade modules are specified to a DRAM t
CASE
of 85°C and -40°C
403
335
Units
t
CK
ps
ps
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
ns
ns
Min
55
70
40
15
15
10
15
2
6
5
0.45
0.45
-0.55
-0.65
-
Max
Min
60
72
42
18
18
12
15
1
6
Max
70K
70K
Clock cycle time
12
10
0.55
0.55
+0.55
+0.65
0.4
12
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.4
t
DQSQ
0.9
0.4
0.72
0
0.25
0.2
0.2
1.1
0.6
1.28
0.9
0.4
0.75
0
0.25
0.2
0.2
1.1
0.6
1.25
t
CK
t
CK
t
CK
ns
t
CK
t
CK
t
CK
Continued on next page
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