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参数资料
| 型号： | W3EG72256MS100AJD3MF |
| 英文描述： | 2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| 中文描述： | 2GB的- 256Mx72 ECC的DDR SDRAM的注册瓦特/锁相环 |
| 文件页数： | 6/14页 |
| 文件大小： | 320K |
| 代理商： | W3EG72256MS100AJD3MF |
White Electronic Designs
W3EG72256S-JD3
-AJD3
PRELIMINARY
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
December 2004
Rev. 2
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes PLL and register power
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
DDR333@CL=2.5*
Max
3155
DDR266@CL=2, 2.5
Max
2885
DDR200@CL=2
Max
2885
Units
mA
Operating Current
I
DD1
3785
3515
3515
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
180
180
180
rnA
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
t
RC
= t
RC
(MIN)
1480
1390
1390
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
630
540
540
mA
I
DD3N
1210
1120
1120
mA
Operating Current
I
DD4R
4235
3875
3875
mA
Operating Current
I
DD4W
4415
4055
4055
rnA
Auto Refresh
Current
Self Refresh Current
Operating Current
I
DD5
6430
6250
6250
mA
I
DD6
I
DD7A
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN); t
=t
(MIN); Address and
control inputs change only during
Active Read or Write commands.
472
9725
472
9005
472
9005
mA
mA
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相关代理商/技术参数 |
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| W3EG72256MS100AJD3MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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| W3EG72256MS100AJD3SG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72256MS133AJD3MF | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72256MS133AJD3MG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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