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参数资料
| 型号： | W3H32M72E-667SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.65 ns, PBGA208 |
| 封装： | 18 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件页数： | 4/31页 |
| 文件大小： | 873K |
| 代理商： | W3H32M72E-667SBC |
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W3H32M72E-XSBX
12
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
July 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specied time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
DLL
Posted CAS#Rtt
out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
BA2
10
11
12
13
02*
14
Poste d CAS# Add itive Laten cy (AL)
0
1
2
3
4
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
1
0
1
E5
0
1
0
1
DLL Enable
Enable (Normal)
Disable (Test/Debug)
E0
15
16
0
1
RDQS Enable
No
Yes
E11
OCD Program
A13
ODS
Rtt
DQS#
0
1
DQS# Enable
Enable
Disable
E10
RDQS
Rtt (nominal)
Rtt Disabled
75Ω
150Ω
50Ω
E2
0
1
0
1
E6
0
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mo de Register Set
Mode Register Set (MR S)
Extended Mode Register (EMR S)
Extended Mode Register (EMR S2)
Extended Mode Register (EMR S3)
E15
0
1
E14
MRS
OCD Operation
OCD Not Supported
Reserved
OCD default state
E7
0
1
0
1
E8
0
1
0
1
E9
0
1
0
1
Output Drive Strength
E1
100%
60%
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is nished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
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PDF描述 |
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| W3H64M16E-400BC | 64M X 16 DDR DRAM, 0.6 ns, PBGA79 |
| W3H64M64E-400SBC | 64M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-400ESI | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-533ES | 64M X 72 DDR DRAM, 0.5 ns, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3H32M72E-667SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-667SBM | 制造商:PMG/Microsemi 功能描述: |
| W3H32M72E-ES | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-ESC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-ESI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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