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参数资料
| 型号： | W3HG64M64EEU665D6IGG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 10/11页 |
| 文件大小： | 166K |
| 代理商： | W3HG64M64EEU665D6IGG |
W3HG64M64EEU-D6
July 2007
Rev. 1
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
SYMBOL
806
665
534
403
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Command
and
Address
ACTIVE to ACTIVE (same bank) command
tRC
TBD
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
ACTIVE to PRECHARGE command
tRAS
TBD
45
70,000
45
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge
time
tDAL
TBD
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
ns
PRECHARGE ALL command period
tRPA
TBD
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
TBD
222
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
ns
Self
Refresh
REFRESH to Active of Refresh to Refresh
command internal
tRFC
TBD
105
ns
Average periodic refresh interval
tREFI
TBD
7.8
μs
Exit self refresh to non-READ command
tXSNR
TBD
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
ODT
ODT turn-on delay
tAOND
TBD
222222
tCK
ODT turn-on
tAON
TBD
tAC (MIN)
tAC (MAX)
+ 700
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 700
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN)
+ 2000
2 x tCK +
tAC (MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
2.5 x
tCK + tAC
(MAX) +
1000
ps
ODT to power-down entry latency
tANPD
TBD
333
tCK
ODT power-down exit latency
tAXPD
TBD
888
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
TBD
222
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
TBD
7 - AL
6 - AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
TBD
222
tCK
CKE minimum high/low time
tCKE
TBD
333
tCK
AC specication is based on
QIMONDA components. Other DRAM manufactures specication may be different.
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相关代理商/技术参数 |
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