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参数资料
| 型号： | W3HG64M64EEU665D6IGG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 8/11页 |
| 文件大小： | 166K |
| 代理商： | W3HG64M64EEU665D6IGG |
W3HG64M64EEU-D6
July 2007
Rev. 1
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol Proposed Conditions
806
665
534
403
Units
ICC0*
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
570
520
440
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
TBD
680
600
480
mA
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
40
30
mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
TBD
320
240
200
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
400
320
260
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
TBD
150
130
100
mA
Slow PDN Exit MRS(12) = 1
TBD
50
40
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
400
320
280
mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,120
760
600
mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK
= tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
TBD
1,040
720
560
mA
ICC5B*
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
1,120
1,040
960
mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING
Normal
TBD
40
32
mA
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
TBD
1,180
1,120
1,040
mA
* Value calculated as one module rank in thes operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reects all module ranks in this operating condition
NOTES:
ICC specications were calculated using
QIMONDA components. Other manufactures DRAMs may have different values.
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