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参数资料
| 型号： | W91030BSG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | TELEPHONE CALLING NO IDENT CKT, PDSO24 |
| 封装： | 300MIL, ROHS COMPLIANT, PLASTIC, SOP-24 |
| 文件页数： | 2/32页 |
| 文件大小： | 245K |
| 代理商： | W91030BSG |
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W91030B
Publication Release Date: Sep. 27, 2005
- 10 -
Revision A2
7.4
FSK Demodulation
The FSK demodulation circuit is enabled when the FSKE signal is high. An enable time is required to
enable the FSK demodulator circuitry after the FSKE signal goes from low to high.
FSK Carrier Detector
The FSK carrier detector provides an indication of the presence of a signal within the FSK frequency
band. If the output amplitude of the FSK bandpass filter is of sufficient magnitude and holds for 8 mS,
the FSK carrier detect output signal FCDN goes low. FCDN will be released if the FSK bandpass filter
output amplitude is of insufficient magnitude for greater than 8 mS. The 8 mS hysteresis of the FSK
carrier detector is to allow for momentary signal drop out after FCDN has been activated.
When FCDN is inactive, the output of the FSK demodulator is ignored by the FSK data output
interface. In mode 0 of the 3-wire FSK data output interface, DCLK DATA and FDRN are all high and
no clock and no data is driven. In mode 1, the internal shift registers are not updated, and FDRN is
inactive (high state). The DATA is undefined if DCLK is clocked.
3-wire FSK Interface
The 3-wire interface, DCLK, DATA and FDRN pins, form the data interface of the FSK demodulation.
The DCLK pin is the data clock which is either generated by the W91030B or by an external device.
The DATA pin is the serial data pin that outputs data to external devices. The FDRN pin is the data
ready signal, also an output from the W91030B to external devices. There are two modes of this 3-
wire interface that can be selected. Mode 0, where the data transfer is initiated by the W91030B
device, or Mode 1, where the data transfer is initiated by an external microcontroller.
Mode 0 (MODE = low):
The W91030B processes the FSK signal and outputs signals on the DCLK, DATA and FDRN pins.
Figure 7-7 shows the timing diagram of the 3-wire signals and the input of the FSK signal in mode 0.
For each received stop and start bit sequence, the device outputs a fixed frequency clock string of 8
pulses on the DCLK pin. Each clock rising edge occurs in the middle of each data bit. DCLK is not
generated for the stop and start bits. The DCLK pin is used as a clock driving signal for a serial to
parallel shift register or for a serial data input for a microcontroller. After the 8-bit data has been shifted
out by the device, the FDRN pin will supply a low pulse to inform the microcontroller to process the 8-
bit data.
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| W91312AS | TELEPHONE DIALER CKT, PDSO20 |
| W91314AS | TELEPHONE DIALER CKT, PDSO20 |
| W91820AN/824AN | TELEPHONE DIALER CKT, PDIP22 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W91031 | 制造商:WINBOND 制造商全称:Winbond 功能描述:LOW POWER CMOS INTERGRATED CIRCUIT |
| W91031S | 制造商:WINBOND 制造商全称:Winbond 功能描述:Calling Line Identifier |
| W91031SG | 功能描述:IC CALL LINE IDENT 24-SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| W91031SG (SA5825) TR | 制造商:Nuvoton Technology Corp 功能描述:FSK DECORDER WITH CALL ON WAIT |
| W91031SG T&R | 制造商:Nuvoton Technology Corp 功能描述:IC CALL LINE IDENT 24-SOIC |
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