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参数资料
| 型号： | W9412FASA-75 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | SODIMM-200 |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 代理商： | W9412FASA-75 |
W9412FASA
Publication Release Date: March 15, 2002
- 11 -
Revision A1
14. SERIAL PRESENCE DETECT EEPROM
The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component.
This nonvolatile storage device contains those data for identifying the module type and various
SDRAM organizations and timing parameters. System read operations to the EEPROM device occur
using the DIMM SCL (clock) and SDA (data) signals, together with SA(2:0) which provide the
EEPROM Device Address.
SPD EEPROM DC Operating Conditions
(VCC = 2.3V
3.6V)
PARAMETER/CONDITION
SYM.
MIN.
MAX.
UNIT
NOTES
Supply Voltage
VCC
2.3
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
VCC x 0.7
VCC +0.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-0.3
VCC x 0.3
V
Output Low Voltage, lout = 3 mA
VOL
0.4
V
IOL = 3 mA
Input Leakage Current, VIN = GND to VCC
ILI
2
uA
Output Leakage Current, VOUT = GND to VCC
ILO
2
uA
Power Supply Current
SCL Clock Frequency = 100 KHz
ICC
1
mA
SPD AC Operating Conditions
(VCC = 2.3V
3.6V)
PARAMETER
SYM.
MIN.
MAX.
UNIT
SCL clock frequency
fSCL
100
KHz
Noise Suppression Time Constant at SCL, SDA Inputs
tI
100
nS
SCL Low to SDA Data Out Valid
tAA
0.2
3.5
S
Time the bus must be free before a new transition can start
tBUF
4.7
S
Start Condition Hold Time
tHD:STA
4.0
S
Clock Low Period
tLOW
4.7
S
Clock High Period
tHIGH
4.0
S
Start Condition Setup Time
tSU:STA
4.7
S
Data in Hold Time
tHD:DAT
0
S
Data in Setup Time
tSU:DAT
250
nS
SDA and SCL Rise time
tR
1
S
SDA and SCL Fall Time
tF
300
nS
Stop Condition Setup Time
tSU:STO
4
S
Data Out Hold Time
tDH
200
nS
Write Cycle Time
tWR
10
mS
Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled,
SDA is allowed to remain
high the bus level pull-up resistor, and the device does not respond to its slave address.
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相关代理商/技术参数 |
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| W9412G2CB | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M 】 4 BANKS 】 32 BITS GDDR SDRAM |
| W9412G2IB | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M × 4 BANKS × 32 BITS GDDR SDRAM |
| W9412G2IB4 | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture; two data transfers per clock cycle |
| W9412G2IB-5 | 制造商:Winbond Electronics Corp 功能描述:8*16 DDR1 |
| W9412G6CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:2M 】 4 BANKS 】 16 BITS DDR SDRAM |
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