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参数资料
| 型号： | W9412FASA-75 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封装： | SODIMM-200 |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 代理商： | W9412FASA-75 |
W9412FASA
- 12 -
15. SPD DATA
FUNCTION SUPPORTED
HEX VALUE
BYTE NO.
FUNCTION DESCRIBED
-7
-75
-7
-75
0
Defines # bytes written into serial memory at
module manufacturer
128 bytes
80h
1
Total # bytes of SPD memory device
256 bytes (2K-bit)
08h
2
Fundamental memory type (FPM, EDO, DRAM..)
DDR SDRAM
07h
3
# Row Addresses on this assembly
13
0Dh
4
# Column Addresses on this assembly
09
09h
5
# Module Rows on this assembly
1 row
01h
6
Data Width of this assembly.
64 bits
40h
7
Data Width continuation
-
00h
8
Voltage interface standard of this assembly
SSTL 2.5V
04h
9
SDRAM Cycle time @CAS latency of 2.5
7 nS
7.5 nS
70h
75h
10
SDRAM Access time @CAS latency of 2.5
+/-0.75 nS
75h
11
DIMM Configuration type (Non-parity, Parity ECC)
Non parity
00h
12
Refresh Rate/Type
7.8
S, support self refresh
82h
13
SDRAM width, Primary DRAM
X 16
10h
14
Error Checking SDRAM data width
None
00h
15
Minimum Clock Delay, Back Random Column
Addresses
TCCD = 1 CLK
01h
16
Burst Lengths supported
2, 4, 8
0Eh
17
#Bank on Each SDRAM device
4 banks
04h
18
CAS# Latencies Supported
2 & 2.5
0Ch
19
CS# Latency
0 CLK
01h
20
Write Latency
1 CLK
02h
21
SDRAM Module Attributes
Differential Clock, Non-
buffered Non–registered &
redundant addressing
20h
22
SDRAM Device Attributes: General
2.5V+/-10% voltage
tolerance, Burst Read, Write,
precharge all, auto precharge
00h
23
SDRAM cycle time @ CAS latency of 2
7.5 nS
10 nS
75h
A0h
24
SDRAM access time @CAS latency of 2
+/-0.75 nS
75h
25
SDRAM cycle time @ CAS latency of 1.5
-
00h
26
SDRAM access time @CAS latency of 1.5
-
00h
27
Precharge to active command period (tRP)
20 nS
50h
28
Active to Active command period (tRRD)
15 nS
3Ch
29
Active to Read/Write command delay time (tRCD)
20 nS
50h
30
Minimum Active to precharge period (tRAS)
45 nS
2Dh
31
Density of each Row on Module
Each row of 128 MB
20h
32
Command and Address signal input setup time
0.9 nS
90h
33
Command and Address signal input hold time
0.9 nS
90h
34
Data signal input setup time
0.5 nS
50h
35
Data signal input hold time
0.5 nS
50h
36 - 61
Superset Information (may be used in future)
-
00h
62
SPD data specification revision
Initial release revision
00h
63
Checksum for Bytes 0 - 62
-
76h
A6h
64 - 128
Unused storage locations
-
00h
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9412G2CB | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M 】 4 BANKS 】 32 BITS GDDR SDRAM |
| W9412G2IB | 制造商:WINBOND 制造商全称:Winbond 功能描述:1M × 4 BANKS × 32 BITS GDDR SDRAM |
| W9412G2IB4 | 制造商:WINBOND 制造商全称:Winbond 功能描述:Double Data Rate architecture; two data transfers per clock cycle |
| W9412G2IB-5 | 制造商:Winbond Electronics Corp 功能描述:8*16 DDR1 |
| W9412G6CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:2M 】 4 BANKS 】 16 BITS DDR SDRAM |
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