参数资料
型号: W972GG8JB-18
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 256M X 8 DDR DRAM, 0.35 ns, PBGA60
封装: 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件页数: 19/86页
文件大小: 1466K
代理商: W972GG8JB-18
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 26 -
Revision A02
7.4.5
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM,
consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as
the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to
insure matched system timing. DM function is disabled, when RDQS / RDQS are enabled by
EMRS(1). (Example timing waveform refer to 10.15 Write operation with Data Mask diagram in
Chapter 10)
7.5
Burst Interrupt
Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by
Write or Precharge Command is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by
Read or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other
Read burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other
Write burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt.
7. Read burst interruption is allowed by a Read with Auto-precharge command.
8. Write burst interruption is allowed by a Write with Auto-precharge command.
9. All command timings are referenced to burst length set in the mode register. They are not
referenced to the actual burst. For example below:
Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising
clock after the un-interrupted burst end and not from the end of the actual burst end.
(Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in
Chapter 10)
相关PDF资料
PDF描述
W9751G6JB-18 32M X 16 DDR DRAM, 0.35 ns, PBGA84
W981204AH-8H 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54
W981216BH75L 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
W981216BH-75 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
W9812G2IH-6 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
相关代理商/技术参数
参数描述
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