参数资料
型号: W972GG8JB
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA60
封装: 11.5 X 11 MM, ROHS COMPLIANT, WBGA-60
文件页数: 24/86页
文件大小: 1466K
代理商: W972GG8JB
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 30 -
Revision A02
7.9.1
Power Down Entry
Two types of Power Down Mode can be performed on the device: Precharge Power Down Mode and
Active Power Down Mode.
If power down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if
power down occurs when there is a row active in any bank, this mode is referred to as Active Power
Down. Entering power down deactivates the input and output buffers, excluding CLK, CLK , ODT and
CKE. Also the DLL is disabled upon entering Precharge Power Down or slow exit Active Power Down,
but the DLL is kept enabled during fast exit Active Power Down.
In power down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the
DDR2 SDRAM, and ODT
should be in a valid state but all other input signals are “Dont Care”. CKE
LOW must be maintained until tCKE has been satisfied. Maximum power down duration is limited by
the refresh requirements of the device, which allows a maximum of 9 x tREFI if maximum posting of
REF is utilized immediately before entering power down. (Example timing waveforms refer to 10.30 to
10.31 Active and Precharged Power Down Mode Entry and Exit diagram in Chapter 10)
7.9.2
Power Down Exit
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or
Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable
command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH.
Power-down exit latency is defined at AC Characteristics table of this data sheet.
7.10 Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic
LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may
change. SDRAM input clock frequency is allowed to change only within minimum and maximum
operating frequency specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before
precharge power down may be exited and DLL must be RESET via MRS command after precharge
power down exit. Depending on new clock frequency an additional MRS or EMRS command may
need to be issued to appropriately set the WR, CL etc
During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to
operate with new clock frequency. (Example timing waveform refer to 10.32 Clock frequency change
in precharge Power Down mode diagram in Chapter 10)
相关PDF资料
PDF描述
W7NCF01GH31CS7BG 64M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF01GH31IS3EG 64M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF08GH21IS3FG 512M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF08GH21IS8JG 512M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF08GH21ISAEG 512M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
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