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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.6 Link Establishment
4.5.5
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration.
The hardware option uses three Global CFG pins that provide control for all ports (see
4.6
Link Establishment
4.6.1
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast
Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5
μs apart. Odd
link pulses (clock pulses) are always present. Even link pulses (data pulses) may also be
present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data,
referred to as a “page”. All devices that support auto-negotiation must implement the
“Base Page”, defined by IEEE 802.3 (registers 4 and 5). The LXT9785/LXT9785E also
supports the optional “Next Page” function (registers 7 and 8).
4.6.1.1
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate
their capabilities to each other. Both sides must receive at least three identical base pages
for negotiation to proceed. Each side finds their highest common capabilities, exchange
more pages, and agree on the operating state of the line.
4.6.1.2
Manual Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via
“Next Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of
negotiation via Next Page exchange. The Next Page exchange uses Register 7 to send
information and Register 8 to receive it. Next Page exchange occurs only if both ends of
the link partners advertise their ability to exchange Next Pages. A special mode has been
added to make manual next page exchange easier for software. When Register 6 “page”
Table 42
Global Hardware Configuration Settings
Desired Mode
CFG
Pin Settings1
Resulting Register Bit Values
AutoNeg
Speed
Duplex
1
2
3
0.12
0.13
0.8
4.8
4.7
4.6
4.5
Disabled
10
Half
Low
0
N/A
Auto-Negotiation
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Full
High
Low
High
1
100
Half
Low
High
Low
1
0
Full
High
1
Enabled
100
Half
High
Low
1
10
0
1
00
Full/Half
High
Low
High
1
0
1
10/100
Half
High
Low
1
0
1
0
1
Full/Half
High
1
0
1
for CFG pin assignments.