
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
210
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
4Pause
0 = The LXT9785/LXT9785E is not Pause capable
1 = The LXT9785/LXT9785E is pause capable
NOTE:
This bit is not affected by Register bit 4.10.
NOTE:
The default for the BGA15 package is 0.
RLSHR4,5
3
Error
0 = No error occurred
1 = Error Occurred (remote fault, RxERCntFUL, FIFO
error, jabber, parallel detect fault)
NOTE:
The register is cleared when the registers that
generated the error condition are read.
R0
2:0
Reserved
Write as 0, ignore on Read.
R
0
Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 2 of 2)
Bit
Name
Description
Type 1
Default2
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
time. Intel recommends that the register status be read on completion of reset.
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
Pause hardware configuration pin. The default for the BGA15 package is 0.