
Contents
16
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
146
Modified Table 69 “Port Configuration Register (Address 16, Hex 10)” (Bits 16.5 and 16.6)
148
Modified Table 71 “Interrupt Enable Register (Address 18, Hex 12)”
168
Added product ordering table and diagram.
Revision Number: 003
Revision Date: April 2001
Page
Description
1
Modified and added new language to front page.
61
Reset: Modified language in first paragraph.
85
Added new section on DTE discovery.
93
Supported JTAG Instructions table: replaced long hit streams with hex.
97
LED Circuit: Modified paragraph language.
97
LED Circuit diagram: Modified diagram.
99
Replaced Typical Fiber Interface diagram.
102
Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency
symbol with “f”.
122
Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = 2.
126
Control Register table: Modified table and table notes.
128
PHY Identification Register 2 (Address 3): Modified table.
128
PHY Identifier Bit Mapping: Modified diagram.
131
Auto-Negotiation Expansion: Modified table and table notes.
133
Port Configuration Register table: Modified table and table notes.
140
Trim Enable Register: Modified table (DTE Discovery).
141
Modified Register Bit Map table.
Revision Number: 005
Revision Date: January 2002
(Sheet 2 of 2)
Page
Description