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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
7.0 Register Definitions
3
SLP_Det
Standard Link Partner Detected.
0 = Standard link partner not discovered; process may not be
complete.
1 = Standard link partner discovered; indication not to turn on
power over the cable.
Note:
This bit is only valid while link is down.
R, LH
0
2
LFIT
Expired
Link Fail Inhibit Timer expiration indicator. Valid only
when SLP_Det = 1.
0 = Link Fail Inhibit Timer has not expired or standard link
partner not discovered
1 = Link Fail Inhibit Timer expired with a standard link partner
detected since last register read or link establishment
R, LH
0
1:0
Reserved
Write as 0, ignore on Read.
R
00
Table 100
Trim Enable Register (Address 27, Hex 1B)
Bit
Name
Description
Type5
Default
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins.
3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin.
4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX
hardware configuration. The BGA15 default = 0.
5. R/W = Read/Write, R = Read Only, LH = Latching High – cleared when read.