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参数资料
| 型号： | WED3DG7264V10D1G |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM MODULE, ZMA144 |
| 封装： | ROHS COMPLIANT, SODIMM-144 |
| 文件页数： | 6/9页 |
| 文件大小： | 249K |
| 代理商： | WED3DG7264V10D1G |
WED3DG7264V-D1
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
July 2005
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
AC FUNCTIONAL CHARACTERISTICS
VCC = 3.3V ±0.3V, 0°C ≤ TA ≤ +70°C
PARAMETER
SYMBOL
7
75/10
UNITS
NOTES
READ/WRITE command to READ/WRITE command
tCCD
11
tCK
17
CKE to clock disable or power-down entry mode
tCKED
11
tCK
14
CKE to clock enable or power-down exit setup mode
tPED
11
tCK
14
DQM to input data delay
tDQD
00
tCK
17
DQM to data mask during WRITEs
tDQM
00
tCK
17
DQM to data high-impedance during READs
tDQZ
22
tCK
17
WRITE command to input data delay
tDWD
00
tCK
17
Data-in to ACTIVE command
tDAL
45
tCK
15, 21
Data-in to PRECHARGE command
tDPL
22
tCK
16, 21
Last data-in to burst STOP command
tBDL
11
tCK
17
Last data-in to new READ/WRITE command
tCDL
11
tCK
17
Last data-in to PRECHARGE command
tRDL
22
tCK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
tMRD
22
tCK
26
Data-out to high-impedance from PRECHARGE command
CL = 3
tROH(3)
33
tCK
17
CL = 2
tROH(2)
22
tCK
17
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