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参数资料
| 型号： | WED3DG7264V10D1G |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM MODULE, ZMA144 |
| 封装： | ROHS COMPLIANT, SODIMM-144 |
| 文件页数： | 7/9页 |
| 文件大小： | 249K |
| 代理商： | WED3DG7264V10D1G |
WED3DG7264V-D1
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
July 2005
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
Notes
1.
All voltages referenced to VSS.
2.
This parameter is sampled. VCC, VCCQ = +3.3V; = 25°C; pin under test biased at
1.4V. f = 1 MHz, TA
3.
IDD is dependent on output loading and cycle rates.Specied values are obtained
with mini-mum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ ≤ 70°C) is TA ensured.
6.
An initial pause of 100μs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
7.
AC characteristics assume tT = 1ns.
8.
In addition to meeting the transition rate specication, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ denes the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. IDD specications are tested after the device is properly initialized.
14. Timing actually specied by tCKS; clock(s) specied as a reference only at minimum
cycle rate.
15. Timing actually specied by tWR plus tRP; clock(s) specied as a reference only at
minimum cycle rate.
16. Timing actually specied by tWR.
17. Required clocks are specied by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease in a proportional amount by the amount
the frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for 75/10 and 7.
22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is dened as a signal
cycling within timing constraints specied for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the rst clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. tAC for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For 75/10, CL = 3, tCK = 7.5ns; For 7, CL = 2, tCK = 7.5ns
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
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相关代理商/技术参数 |
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| WED3DG7264V75D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 SDRAM, UNBUFFERED w/PLL |
| WED3DG7264V7D1 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 SDRAM, UNBUFFERED w/PLL |
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