参数资料
型号: WED7G320IDE33ADC25
厂商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分类: PROM
英文描述: 18M X 16 FLASH 3.3V PROM, DMA144
封装: SO-DIMM-144
文件页数: 6/8页
文件大小: 167K
代理商: WED7G320IDE33ADC25
FM
S6400-
1
D
u
al-
C
hannel
Video
D
river
wit
h
In
te
grat
ed
Filt
ers
and
C
o
mposit
e
Video
Summer
2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6400-1 Rev. 1.0.1
6
Application Information
Functional Description
This product is a two-channel monolithic, continuous-
time, video filter designed for reconstructing the
luminance and chrominance signals from an S-Video
D/A source. Composite video output is generated by
summing the Y and C outputs. The chip is designed to
have AC-coupled inputs and works equally well with
AC- or DC-coupled outputs.
The reconstruction filters provide a 5
th-order Butterworth
response with group delay equalization. This provides a
maximally flat response in terms of delay and
amplitude. Each of the three outputs is capable of
driving 2VPP into a 75 load.
All channels are clamped during the sync interval to set
the appropriate minimum output DC level. With this
operation, the effective input time constant is greatly
reduced, which allows for the use of small low-cost
coupling capacitors. The net effect is that the input
settles to 10mV in 10ms for any DC shifts present in the
input video signal.
In most applications, the input coupling capacitors are
0.1μF. The Y and C inputs typically sink 1μA of current
during active video, which normally tilts a horizontal line
by 2mV at the Y output. During sync, the clamp restores
this leakage current by sourcing an average of 20μA
over the clamp interval. Any change in the coupling
capacitor values affects the amount of tilt per line. Any
reduction in tilt comes with an increase in settling time.
Luminance (Y) I/O
The typical Luma input is driven by either a low-
impedance source of 1VPP or the output of a 75-
terminated line driven by the output of a current DAC. In
either case, the input must be capacitively coupled to
allow the sync detect and DC restore circuitry to operate
properly.
All outputs are capable of driving 2VPP, AC or DC
coupled, into either a single or dual video load. A single
video load consists of a series-75, impedance-
matching resistor connected to a terminated 75 line.
This presents a total of 150 of loading to the part. A
dual load is two of these in parallel, which presents a
total of 75 to the part.
Channel gain of 0dB on all channels is selected by tying
pin 2 to ground. Channel gain of 6dB on all channels is
selected by tying pin 2 to VCC. Both gain settings
assume standard input video levels of 1VPP.
Chrominance (C) I/O
The chrominance input can be driven in the same
manner as the luminance input, but is typically only a
0.7Vpp signal. Since the chrominance signal doesn't
contain any DC content, the output signal can be AC
coupled using as small as a 0.1μF capacitor if DC
coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other
outputs.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency
performance
and
thermal
characteristics. Fairchild offers a demonstration board,
FMS6400DEMO, to use as a guide for layout and to aid
in
device
testing
and
characterization.
The
FMS6400DEMO is a four-layer board with a full power
and ground plane. For optimum results, follow the steps
below as a basis for high frequency layout:
Include 10μF and 0.1μF ceramic bypass
capacitors.
Place the 10μF capacitor within 0.75 inches of the
power pin.
Place the 0.1μF capacitor within 0.1 inches of the
power pin.
If using DC-coupled outputs, use a large ground
plane to help dissipate heat.
Minimize all trace lengths to reduce series
inductances.
Output Considerations
The FMS6400-1 outputs are DC offset from the input by
150mV. Therefore, VOUT = 2*VIN DC+150mV. This offset
is required to obtain optimal performance from the
output driver and is held at the minimum value to
decrease the standing DC current into the load. Since
the FMS6400-1 has a 2x (6dB) gain, the output is
typically connected via a 75-series back-matching
resistor, followed by the 75 video cable. Due to the
inherent divide by two of this configuration, the blanking
level at the load of the video signal is always less then
1V. When AC-coupling the output, ensure that the
coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time
distortion (video tilt) is kept as low as possible.
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input being driven. To obtain the highest
quality output video signal, the series termination
resistor must be placed as close to the output pin as
possible. This greatly reduces the parasitic capacitance
and inductance effect on the output driver. The distance
from the device pin to the series termination resistor
should be no greater than 0.1 inches.
Figure 4. Distance from Device Pin to Series
Termination Resistor
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