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| 型号： | WJLXT971ALC.A4SE000 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 12/116页 |
| 文件大小： | 1172K |
| 代理商： | WJLXT971ALC.A4SE000 |
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Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
19
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
8.
MII Pins Not Three-Stateable
Problem:
In hardware power-down mode, the receive clock MDINT pins do not go into a high-impedance
state or are not three-stated.
Implication:
In hardware power-down mode, the receive clock (RxClk) and the MDINT pins are continuously
driven. The transmit clock will be in a true three-state condition. However, the LXT971A and
LXT972A Transceivers continue to source a receive clock.
Workaround:
None.
Status:
This erratum has been previously fixed.
9.
100 M External Loopback Using Short Cable Length
Problem:
Link may not occur in applications requiring a short external looping plug (looping TPFO to TPFI)
with cable lengths typically less than 2 feet.
Implication:
During external loopback operations requiring a line-loop length less than two feet, the LXT971A
and LXT972A Transceivers input-receiver reference levels may incorrectly slice the twisted-pair
signal, causing a loss of link.
Workaround:
None.
Status:
This erratum has been previously fixed.
10.
10BASE-T Data Inversion
Problem:
If jitter on the twisted-pair data occurs within a time window relative internally to the DPLL
Reference Clock and remains constant, inverted RxData can occur.
Implication:
When the receive twisted-pair data jitters, the LXT971A and LXT972A Transceivers may pass
errored data to the Reconciliation Sublayer. This errored data would be calculated as CRC errors at
the MAC and the RXER signal/bit would be active.
Workaround:
None.
Status:
This erratum has been previously fixed.
11.
Power Cycling and JTAG TRST Reset Pin
Problem:
Power-on cycling may cause the LXT971A and LXT972A Transceivers to hang in an unknown
state due to the improper reset of some internal JTAG control flip-flops.
Implication:
Some internal JTAG flip-flops may not be reset properly, causing the input and output steering
muxes to be selected incorrectly. This incorrect selection may disable any of the digital, MII signal
outputs and inputs.
Workaround:
Designs not using JTAG should tie the TRST pin directly to GND.
Designs using the 5-signal option should tie the TRST pin to GND through a resistor. The
suggested value for this resistor is 20 k
. A 20 k resistor to GND is strong enough to pull down
the internal, weak pull-up to a logic 0 for normal operation. This pull down also allows a JTAG tap
controller to operate successfully and overcome the pull-up and pull-down resistors.
Designs using the 4-signal option and not using the TRST pin for reset should use a 20 k
pull-
down resistor from TRST to GND and control the JTAG TRST pin, accordingly.
Designs using the LXT971A or LXT972A Transceivers require a new BSDL file that may be
found on the Intel website (www.intel.com).
Status:
This erratum has been previously fixed.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT971ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT971ALE.A4 | 功能描述:IC XCVR 3V 2-SPEED ETHER 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857343 | 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:发射器 驱动器/接收器数:4/0 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857346 | 制造商:Cortina Systems Inc 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP T/R |
| WJLXT971CA4 | 制造商:Intel 功能描述: |
| WJLXT972ALC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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