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| 型号： | WJLXT971ALC.A4SE000 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 14/116页 |
| 文件大小： | 1172K |
| 代理商： | WJLXT971ALC.A4SE000 |
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20
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
12.
Switching Clocks from 100 Mbps to 10 Mbps Prior to End-of-Packet
Problem:
Switching clocks from 100 Mbps to 10 Mbps prior to the End-of-Packet (EOP), as the PLL
transitions to its reset state, can cause the output to become random and unknown, and result in the
corruption of the last nibble of the CRC in the receive packet.
Implication:
A CRC error occurs randomly on a small percentage of devices and can result in an error rate up to
10 ppm.
Workaround:
None.
Status:
This erratum has been previously fixed.
13.
Changing Advertised Duplex While Link Is Up
Problem:
Writing to Register bits 4.9:5, which control duplex mode advertisement while link is up and auto-
negotiation is enabled, immediately changes the PHY mode of operation to the new duplex mode.
When written, the values in this register are not intended to affect PHY operation until a new auto-
negotiation cycle is completed.
Implication:
A possible mixed-duplex operation will exist during the time between Register bits 4.9:5 writes
and the start of a new auto-negotiation process.
Workaround:
Write Register bits 4.9:5 immediately before the start of a new auto-negotiation process.
Status:
There are no plans to fix this erratum.
14.
Far-End Fault Reporting
Problem:
If a link partner continuously sends successive Far-End Fault (FEF) codes (three sets of 84 1s
followed by a 0), the LXT971A/LXT972A Transceiver sets the Remote Fault bit High (Register bit
1.4 = 1) and drops link (Register bit 1.2 = 0). Register 1.4 is cleared after a Read and is not set High
again while the Far-End Fault signal is present.
Implication:
Implication:
If the MAC reads Register bit 1.4 more than once under a continuous Far-End Fault
condition, a Far-End Fault is not indicated after the first Read.
Workaround:
Once a remote fault has been indicated by Register bit 1.4 = 1, the following sequence can be used
to monitor the remote-fault status.
Managed Systems:
1. Write Register 0 = 0x6100. This forces the port to 100 Mbps full-duplex internal loopback,
link is up, Register bit 1.2 = 1, and Register bit 1.4 = 0.
2. Wait approximately 100 mS.
3. Write Register 0 = 0x2100. This forces the port into 100 Mbps full-duplex. If Far-End Fault is
present, Register bit 1.4 = 1 indicates Far-End Fault and Register bit 1.2 = 0 indicates link is
down.
Status:
There are no plans to fix this erratum.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT971ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALE.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT971ALE.A4 | 功能描述:IC XCVR 3V 2-SPEED ETHER 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857343 | 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:发射器 驱动器/接收器数:4/0 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT971ALE.A4-857346 | 制造商:Cortina Systems Inc 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP T/R |
| WJLXT971CA4 | 制造商:Intel 功能描述: |
| WJLXT972ALC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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