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| 型号： | WJLXT972ALC.A4-857341 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 10/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT972ALC.A4-857341 |
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Page 18
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
4.0 Signal Descriptions
Table 9
LXT972A: Configuration and LED Driver Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
Note:
Implement 10 k
Ω pull-up/pull-down resistors if LEDs are not used in the design.
5
6
TxSLEW0
TxSLEW1
I
Tx Output Slew Controls 0 and 1.
These pins select the TX output slew rate (rise and fall time) as follows:
TxSLEW1
TxSLEW0
Slew Rate (Rise and Fall
Time)
0
3.0 ns
0
1
3.4 ns
1
0
3.9 ns
1
4.4 ns
4
RESET_L
I
Reset.
This active Low input is ORed with the control register Reset bit (register
bit 0.15). The PHY reset cycle is extended to 258
μs (nominal) after reset
is de-asserted.
17
RBIAS
AI
Reference Current Bias.
This pin provides bias current for the internal circuitry. Must be tied to
ground through a 22.1 k
Ω, 1% resistor.
33
PAUSE
I
Pause.
When set High, the PHY advertises Pause capabilities during auto-
negotiation.
39
PWRDWN
I
Power Down.
When set High, this pin puts the PHY in a power-down mode.
1
2
REFCLK/XI
XO
I and
O
Reference Clock Input / Crystal Input and Crystal Output.
A 25 MHz crystal oscillator circuit can be connected across XI and XO. A
clock can also be used at XI. Refer to Section 5.3.2, Clock
Requirements, on page 26 in the Functional Description section.
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
LED Drivers 1-3.
These pins drive LED indicators. Each LED can display one of several
available status conditions as selected by the LED Configuration
Register. (For details, see Table 53, LED Configuration Register -
Configuration Inputs 1-3.
These pins also provide initial configuration settings. (For details, see
Table 13, Hardware Configuration Settings, on page 28.)
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